Inventor
G JEEVABHARATHI
IN4 patents
Patents
4 patentsUS12261609B1Mar 25, 2025
Inter-PLL communication in a multi-PLL environment
SHAOXING YUANFANG SEMICONDUCTOR CO LTD1 citations58
US12149255B2Nov 19, 2024
Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable
SHAOXING YUANFANG SEMICONDUCTOR CO LTD0 citations57
US11967965B2Apr 23, 2024
Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable
SHAOXING YUANFANG SEMICONDUCTOR CO LTD0 citations57
US11923864B2Mar 5, 2024
Fast switching of output frequency of a phase locked loop (PLL)
SHAOXING YUANFANG SEMICONDUCTOR CO LTD0 citations47