Inventor
HERDRICH ANDREW
US23 patents
⚠️ This page may combine multiple inventors who share the name “HERDRICH ANDREW”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
21 patentsUS9235256B2Jan 12, 2016
Methods and apparatuses for controlling thread contention
INTEL CORP8 citations92
US8775834B2Jul 8, 2014
Methods and apparatuses for controlling thread contention
INTEL CORP8 citations92
US9218046B2Dec 22, 2015
Methods and apparatuses for controlling thread contention
INTEL CORP4 citations83
US8924748B2Dec 30, 2014
Methods and apparatuses for controlling thread contention
INTEL CORP5 citations83
US8738942B2May 27, 2014
Methods and apparatuses for controlling thread contention
INTEL CORP5 citations83
US10630315B2Apr 21, 2020
Technologies for applying a redundancy encoding scheme to segmented network packets
INTEL CORP5 citations82
US10303504B2May 28, 2019
Systems, methods, and apparatuses for resource monitoring
INTEL CORP2 citations73
US10613876B2Apr 7, 2020
Methods and apparatuses for controlling thread contention
INTEL CORP1 citations72
US11515890B2Nov 29, 2022
Technologies for applying a redundancy encoding scheme to segmented network packets
INTEL CORP1 citations71
US10216668B2Feb 26, 2019
Technologies for a distributed hardware queue manager
INTEL CORP5 citations70
US12093100B2Sep 17, 2024
Hierarchical power management apparatus and method
INTEL CORP3 citations69
US10866834B2Dec 15, 2020
Apparatus, method, and system for ensuring quality of service for multi-threading processor cores
INTEL CORP3 citations65
US11531562B2Dec 20, 2022
Systems, methods, and apparatuses for resource monitoring
INTEL CORP0 citations62
US12229069B2Feb 18, 2025
Accelerator controller hub
INTEL CORP0 citations61
US11146288B2Oct 12, 2021
Technologies for applying a redundancy encoding scheme to segmented network packets
INTEL CORP0 citations61
US10929323B2Feb 23, 2021
Multi-core communication acceleration using hardware queue device
INTEL CORP1 citations61
US11121940B2Sep 14, 2021
Techniques to meet quality of service requirements for a fabric point to point connection
INTEL CORP0 citations52
US9715397B2Jul 25, 2017
Methods and apparatuses for controlling thread contention
INTEL CORP0 citations51
US12487928B2Dec 2, 2025
Two-stage cache partitioning
INTEL CORP0 citations50
US12210434B2Jan 28, 2025
Apparatus and method for a closed-loop dynamic resource allocation control framework
INTEL CORP0 citations50
US12198186B2Jan 14, 2025
Systems, apparatuses, and methods for resource bandwidth enforcement
INTEL CORP0 citations50