Inventor

GLEW ANDREW F

US108 patents

⚠️ This page may combine multiple inventors who share the name “GLEW ANDREW F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GLEW ANDREW F

INTEL CORP

Method and apparatus for handling speculative memory access operations

Method and apparatus for processing memory-type information within a microprocessor

Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer

Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state

Method and apparatus for blocking execution of and storing load operations during their execution

Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner

Speculative and committed resource files in an out-of-order processor

Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file

Method and apparatus for dynamic allocation of multiple buffers in a processor

Method and apparatus for implementing a single clock cycle line replacement in a data cache unit

Method for executing instructions that operate on different data types stored in the same single logical register file

Flag renaming and flag masks within register alias table

Method and apparatus for hazard detection and distraction avoidance for a vehicle

Mechanism for efficiently overlapping multiple operand types in a microprocessor

Computer implemented method for transferring packed data between register files and memory

Method and apparatus for changing flow of control in a processor

Method and apparatus for predicting, clearing and redirecting unpredicted changes in instruction flow in a microprocessor

Method and apparatus for blocking execution of and storing load operations during their execution

Executing different instructions that cause different data type operations to be performed on single logical register file

Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor

Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers

Write combining buffer for sequentially addressed partial line operations originating from a single instruction

Translation lookaside buffer that is non-blocking in response to a miss for use within a microprocessor capable of processing speculative instructions

Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system

Branch target buffer for dynamically predicting branch instruction outcomes using a predicted branch history

Method and apparatus for loading and storing misaligned data on an out-of-order execution computer system

Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges

Apparatus and method for renaming registers in a processor and resolving data dependencies thereof

Idiom recognizer within a register alias table

Methods and apparatus for determining the next instruction pointer in an out-of-order execution computer system

Coordinating speculative and committed state register source data and immediate source data in a processor

Partial width stalls within register alias table

Apparatus and method for maintaining processing consistency in a computer system having multiple processors

Method and apparatus for caching system management mode information with other information

Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed

Floating point register alias table FXCH and retirement floating point register array

Apparatus and method for handling string operations in a pipelined processor

Stalling predicted prefetch to memory location identified as uncacheable using dummy stall instruction until branch speculation resolution

Method and apparatus for performing operations based upon the addresses of microinstructions

Method and apparatus for loading a segment register in a microprocessor capable of operating in multiple modes

System providing video compression/encoding for communications across a network

Exception handling in a processor that performs speculative out-of-order instruction execution

Segment register renaming in an out of order processor

Centralized performance monitoring architecture

GLEW ANDREW F

Fine-grained security in federated data sets

Instruction set adapted for security risk monitoring

GERRITY DANIEL A

Intrusion detection using taint accumulation

Data handling apparatus adapted for scheduling operations according to resource allocation based on entitlement

(unassigned)

Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations

INTEL CORPORAITON

Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers