Inventor

COLWELL ROBERT P

US40 patents

⚠️ This page may combine multiple inventors who share the name “COLWELL ROBERT P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

COLWELL ROBERT P

INTEL CORP

Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer

Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor

Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state

Speculative and committed resource files in an out-of-order processor

Method and apparatus for dynamic allocation of multiple buffers in a processor

Flag renaming and flag masks within register alias table

Mechanism for efficiently overlapping multiple operand types in a microprocessor

Method and apparatus for changing flow of control in a processor

Method and apparatus for predicting, clearing and redirecting unpredicted changes in instruction flow in a microprocessor

Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor

Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges

Apparatus and method for renaming registers in a processor and resolving data dependencies thereof

Idiom recognizer within a register alias table

Coordinating speculative and committed state register source data and immediate source data in a processor

Partial width stalls within register alias table

Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed

Floating point register alias table FXCH and retirement floating point register array

Method and apparatus for maximum throughput scheduling of dependent operations in a pipelined processor

Exception handling in a processor that performs speculative out-of-order instruction execution

Register alias table update to indicate architecturally visible state

Computer system with self-consistent ordering mechanism

Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming

Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path

Hybrid execution unit for complex microprocessor

Method and apparatus for implementing a non-blocking translation lookaside buffer

Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming

N-wide bypass for data dependencies within register alias table

Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution

High byte right-shift apparatus with a register alias table

Self-monitoring distributed hardware systems

Data processor with circuitry for handling pointers associated with a register exchange operation

Integer and floating point register alias table within processor device

Methods and apparatus for determining operating characteristics of a memory element based on its physical location

Entry allocation in a circular buffer

Method and apparatus for providing address-size backward compatibility in a processor using segmented memory

DIGITAL EQUIPMENT CORP

Instruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatus

Instruction storage method with a compressed format using a mask word

High bandwidth multiple computer bus apparatus

MULTIFLOW COMPUTER INC

Hierarchical priority branch handling for parallel execution in a parallel processor

Virtual address table look aside buffer miss recovery method and apparatus