Inventor

FETTERMAN MICHAEL A

US41 patents

⚠️ This page may combine multiple inventors who share the name “FETTERMAN MICHAEL A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FETTERMAN MICHAEL A

INTEL CORP

Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer

Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state

Speculative and committed resource files in an out-of-order processor

Method and apparatus for resolving return from subroutine instructions in a computer processor

Method and apparatus for implementing a set-associative branch target buffer

Circuit and method for scheduling instructions by predicting future availability of resources required for execution

Method and apparatus for dynamic allocation of multiple buffers in a processor

Flag renaming and flag masks within register alias table

Mechanism for efficiently overlapping multiple operand types in a microprocessor

Method and apparatus for changing flow of control in a processor

Method and apparatus for predicting, clearing and redirecting unpredicted changes in instruction flow in a microprocessor

Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor

Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges

Methods and apparatus for determining the next instruction pointer in an out-of-order execution computer system

Coordinating speculative and committed state register source data and immediate source data in a processor

Method and apparatus for generating event handler vectors based on both operating mode and event type

Circuit and method for scheduling instructions by predicting future availability of resources required for execution

Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed

Apparatus and method for handling string operations in a pipelined processor

Method and apparatus for pipeline streamlining where resources are immediate or certainly retired

Method and apparatus for maximum throughput scheduling of dependent operations in a pipelined processor

Exception handling in a processor that performs speculative out-of-order instruction execution

Segment register renaming in an out of order processor

Register alias table update to indicate architecturally visible state

Computer system with self-consistent ordering mechanism

Method and apparatus for dispatching and executing a load operation to memory

Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming

Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path

Hybrid execution unit for complex microprocessor

Method and apparatus for implementing a non-blocking translation lookaside buffer

Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming

Apparatus for pipeline streamlining where resources are immediate or certainly retired

Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution

Method and apparatus for combining micro-operations to process immediate data

Circuit and method for scheduling instructions by predicting future availability of resources required for execution

Instruction pointer limits in processor that performs speculative out-of-order instruction execution

Entry allocation in a circular buffer

Method and apparatus for executing and dispatching store operations in a computer system

Method and apparatus for providing address-size backward compatibility in a processor using segmented memory

Method and apparatus for representation of an address in canonical form

NVIDIA CORP

Out of order memory request tracking structure and technique