Inventor
MEANEY PATRICK JAMES
US18 patents
Patents
18 patentsUS5784383AJul 21, 1998
Apparatus for identifying SMP bus transfer errors
IBM37 citations92
US5774481AJun 30, 1998
Reduced gate error detection and correction circuit
IBM31 citations92
US6163857ADec 19, 2000
Computer system UE recovery logic
IBM18 citations83
US6055660AApr 25, 2000
Method for identifying SMP bus transfer errors
IBM18 citations83
US11200119B2Dec 14, 2021
Low latency availability in degraded redundant array of independent memory
IBM4 citations72
US11646861B2May 9, 2023
Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modes
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US11520659B2Dec 6, 2022
Refresh-hiding memory system staggered refresh
IBM0 citations62
US11609817B2Mar 21, 2023
Low latency availability in degraded redundant array of independent memory
IBM0 citations61
US11907074B2Feb 20, 2024
Low-latency deserializer having fine granularity and defective-lane compensation
IBM0 citations60
US7987400B2Jul 26, 2011
Method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy
IBM6 citations60
US6038626AMar 14, 2000
Method for controlling data transfers and routing
IBM3 citations60
US5996040ANov 30, 1999
Scalable, modular selector system
IBM6 citations60
US6195757B1Feb 27, 2001
Method for supporting 1½ cycle data paths via PLL based clock system
IBM2 citations59
US12188979B2Jan 7, 2025
Error protection analysis of an integrated circuit
IBM0 citations56
US11960426B2Apr 16, 2024
Cable pair concurrent servicing
IBM0 citations47
US7979838B2Jul 12, 2011
Method of automating creation of a clock control distribution network in an integrated circuit floorplan
IBM0 citations46
US12380004B2Aug 5, 2025
Dynamic multi-lane degrade capability to facilitate uninterrupted service
IBM0 citations45
US7702972B2Apr 20, 2010
Method and apparatus for SRAM macro sparing in computer chips
IBM1 citations43