Inventor

HAGERSTEN ERIK E

US64 patents

Patents

50 patents

US5887138AMar 23, 1999

Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes

SUN MICROSYSTEMS INC168 citations99

US5862357AJan 19, 1999

Multiprocessing computer system employing a cluster communication launching and addressing mechanism

SUN MICROSYSTEMS INC62 citations97

US5958019ASep 28, 1999

Multiprocessing system configured to perform synchronization operations

SUN MICROSYSTEMS INC103 citations97

US6826660B2Nov 30, 2004

Hierarchical SMP computer system

SUN MICROSYSTEMS INC40 citations96

US6578071B2Jun 10, 2003

Repeater for use in a shared memory computing system

SUN MICROSYSTEMS INC37 citations96

US6536000B1Mar 18, 2003

Communication error reporting mechanism in a multiprocessing computer system

SUN MICROSYSTEMS INC67 citations96

US6351795B1Feb 26, 2002

Selective address translation in coherent memory replication

SUN MICROSYSTEMS INC32 citations96

US6332165B1Dec 18, 2001

Multiprocessor computer system employing a mechanism for routing communication traffic through a cluster node having a slice of memory directed for pass through transactions

SUN MICROSYSTEMS INC29 citations96

US6240501B1May 29, 2001

Cache-less address translation

SUN MICROSYSTEMS INC61 citations96

US6226671B1May 1, 2001

Shared memory system for symmetric multiprocessor systems

SUN MICROSYSTEMS INC50 citations96

US5983326ANov 9, 1999

Multiprocessing system including an enhanced blocking mechanism for read-to-share-transactions in a NUMA mode

SUN MICROSYSTEMS INC72 citations96

US5893149AApr 6, 1999

Flushing of cache memory in a computer system

SUN MICROSYSTEMS INC75 citations96

US5881303AMar 9, 1999

Multiprocessing system configured to perform prefetch coherency activity with separate reissue queue for each processing subnode

SUN MICROSYSTEMS INC59 citations96

US5878268AMar 2, 1999

Multiprocessing system configured to store coherency state within multiple subnodes of a processing node

SUN MICROSYSTEMS INC89 citations96

US5860159AJan 12, 1999

Multiprocessing system including an apparatus for optimizing spin--lock operations

SUN MICROSYSTEMS INC71 citations96

US5852716ADec 22, 1998

Split-SMP computer system with local domains and a top repeater that distinguishes local and global transactions

SUN MICROSYSTEMS INC80 citations96

US5848254ADec 8, 1998

Multiprocessing system using an access to a second memory space to initiate software controlled data prefetch into a first address space

SUN MICROSYSTEMS INC58 citations96

US5796605AAug 18, 1998

Extended symmetrical multiprocessor address mapping

SUN MICROSYSTEMS INC58 citations96

US5734922AMar 31, 1998

Multiprocessing system configured to detect and efficiently provide for migratory data access patterns

SUN MICROSYSTEMS INC63 citations96

US6449700B2Sep 10, 2002

Multiprocessing computer system employing a cluster protection mechanism

SUN MICROSYSTEMS INC48 citations95

US6401174B1Jun 4, 2002

Multiprocessing computer system employing a cluster communication error reporting mechanism

SUN MICROSYSTEMS INC36 citations95

US5862316AJan 19, 1999

Multiprocessing system having coherency-related error logging capabilities

SUN MICROSYSTEMS INC90 citations95

US6760786B2Jul 6, 2004

Multiprocessing system configured to perform efficient block copy operations

SUN MICROSYSTEMS INC27 citations93

US6446185B2Sep 3, 2002

Selective address translation in coherent memory replication

SUN MICROSYSTEMS INC22 citations93

US6332169B1Dec 18, 2001

Multiprocessing system configured to perform efficient block copy operations

SUN MICROSYSTEMS INC23 citations93

US5923847AJul 13, 1999

Split-SMP computer system configured to operate in a protected mode having repeater which inhibits transaction to local address partiton

SUN MICROSYSTEMS INC44 citations93

US5754877AMay 19, 1998

Extended symmetrical multiprocessor architecture

SUN MICROSYSTEMS INC47 citations93

US5950226ASep 7, 1999

Multiprocessing system employing a three-hop communication protocol

SUN MICROSYSTEMS INC30 citations92

US5940860AAug 17, 1999

Methods and apparatus for substantially memory-less coherence transformer for connecting computer node coherence domains

SUN MICROSYSTEMS INC27 citations92

US5897657AApr 27, 1999

Multiprocessing system employing a coherency protocol including a reply count

SUN MICROSYSTEMS INC46 citations92

US5873117AFeb 16, 1999

Method and apparatus for a directory-less memory access protocol in a distributed shared memory computer system

SUN MICROSYSTEMS INC20 citations92

US5864671AJan 26, 1999

Hybrid memory access protocol for servicing memory access request by ascertaining whether the memory block is currently cached in determining which protocols to be used

SUN MICROSYSTEMS INC39 citations92

US5860109AJan 12, 1999

Methods and apparatus for a coherence transformer for connecting computer system coherence domains

SUN MICROSYSTEMS INC22 citations92

US5835906ANov 10, 1998

Methods and apparatus for sharing stored data objects in a computer system

SUN MICROSYSTEMS INC51 citations92

US5829034AOct 27, 1998

Method and apparatus for a coherence transformer with limited memory for connecting computer system coherence domains

SUN MICROSYSTEMS INC39 citations92

US7237068B2Jun 26, 2007

Computer system employing bundled prefetching and null-data packet transmission

SUN MICROSYSTEMS INC25 citations86

US7529844B2May 5, 2009

Multiprocessing systems employing hierarchical spin locks

SUN MICROSYSTEMS INC15 citations84

US7529893B2May 5, 2009

Multi-node system with split ownership and access right coherence mechanism

SUN MICROSYSTEMS INC11 citations84

US5802563ASep 1, 1998

Efficient storage of data in computer system with multiple cache levels

SUN MICROSYSTEMS INC17 citations84

US6654866B2Nov 25, 2003

Skewed finite hashing function

SUN MICROSYSTEMS INC11 citations82

US6618799B2Sep 9, 2003

Selective address translation in coherent memory replication

SUN MICROSYSTEMS INC9 citations82

US6308246B1Oct 23, 2001

Skewed finite hashing function

SUN MICROSYSTEMS INC8 citations82

US7080213B2Jul 18, 2006

System and method for reducing shared memory write overhead in multiprocessor systems

SUN MICROSYSTEMS INC16 citations79

US7363462B2Apr 22, 2008

Performing virtual to global address translation in processing subsystem

SUN MICROSYSTEMS INC7 citations74

US5903907AMay 11, 1999

Skip-level write-through in a multi-level memory of a computer system

SUN MICROSYSTEMS INC10 citations74

Showing the top 50 of 64 patents by PatentIndex Score.

HAGERSTEN ERIK E

Patents

Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes

Hierarchical SMP computer system

Multiprocessing system configured to perform efficient write operations

Efficient allocation of cache memory space in a computer system

Multiprocessing system configured to perform efficient block copy operations

Hybrid memory access protocol in a distributed shared memory computer system

Multiprocessing computer system employing a cluster communication launching and addressing mechanism

Multiprocessing system configured to perform synchronization operations

Hierarchical SMP computer system

Repeater for use in a shared memory computing system

Communication error reporting mechanism in a multiprocessing computer system

Selective address translation in coherent memory replication

Multiprocessor computer system employing a mechanism for routing communication traffic through a cluster node having a slice of memory directed for pass through transactions

Cache-less address translation

Shared memory system for symmetric multiprocessor systems

Multiprocessing system including an enhanced blocking mechanism for read-to-share-transactions in a NUMA mode

Flushing of cache memory in a computer system

Multiprocessing system configured to perform prefetch coherency activity with separate reissue queue for each processing subnode

Multiprocessing system configured to store coherency state within multiple subnodes of a processing node

Multiprocessing system including an apparatus for optimizing spin--lock operations

Split-SMP computer system with local domains and a top repeater that distinguishes local and global transactions

Multiprocessing system using an access to a second memory space to initiate software controlled data prefetch into a first address space

Extended symmetrical multiprocessor address mapping

Multiprocessing system configured to detect and efficiently provide for migratory data access patterns

Multiprocessing computer system employing a cluster protection mechanism

Multiprocessing computer system employing a cluster communication error reporting mechanism

Multiprocessing system having coherency-related error logging capabilities

Multiprocessing system configured to perform efficient block copy operations

Selective address translation in coherent memory replication

Multiprocessing system configured to perform efficient block copy operations

Split-SMP computer system configured to operate in a protected mode having repeater which inhibits transaction to local address partiton

Extended symmetrical multiprocessor architecture

Multiprocessing system employing a three-hop communication protocol

Methods and apparatus for substantially memory-less coherence transformer for connecting computer node coherence domains

Multiprocessing system employing a coherency protocol including a reply count

Method and apparatus for a directory-less memory access protocol in a distributed shared memory computer system

Hybrid memory access protocol for servicing memory access request by ascertaining whether the memory block is currently cached in determining which protocols to be used

Methods and apparatus for a coherence transformer for connecting computer system coherence domains

Methods and apparatus for sharing stored data objects in a computer system

Method and apparatus for a coherence transformer with limited memory for connecting computer system coherence domains

Computer system employing bundled prefetching and null-data packet transmission

Multiprocessing systems employing hierarchical spin locks

Multi-node system with split ownership and access right coherence mechanism

Efficient storage of data in computer system with multiple cache levels

Skewed finite hashing function

Selective address translation in coherent memory replication

Skewed finite hashing function

System and method for reducing shared memory write overhead in multiprocessor systems

Performing virtual to global address translation in processing subsystem

Skip-level write-through in a multi-level memory of a computer system