Inventor

KAWA JAMIL

US70 patents

⚠️ This page may combine multiple inventors who share the name “KAWA JAMIL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KAWA JAMIL

SYNOPSYS INC

One-time programmable memory using rupturing of gate insulation

Cells having transistors and interconnects including nanowires or 2D material strips

FinFET cell architecture with insulator structure

FinFET cell architecture with power traces

Memory cells including vertical nanowire transistors

Memory cell including vertical transistors and horizontal nanowire bit lines

FinFET cell architecture with power traces

Nanowire or 2D material strips interconnects in an integrated circuit cell

Array with intercell conductors including nanowires or 2D material strips

Nanowire or 2D material strips interconnects in an integrated circuit cell

FinFET cell architecture with power traces

Method and apparatus for floating or applying voltage to a well of an integrated circuit

Method and apparatus for designing an integrated circuit using a mask-programmable fabric

Read-write architecture for low voltage SRAMs

Josephson junction structures

Josephson junction structures

FinFET cell architecture with insulator structure

Logic timing and reliability repair for nanowire circuits

Enhancing memory yield and performance through utilizing nanowire self-heating

Cells having transistors and interconnects including nanowires or 2D material strips

Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits

Electrostatic-discharge protection using a micro-electromechanical-system switch

Single flux quantum circuit that includes a sequencing circuit

Circuit skew compensation trigger system

Substrates and transistors with 2D material channels on 3D geometries

Evaluation of thermal instability stress testing

Negative bias thermal instability stress testing of transistors

Reset before write architecture and method

Power harvesting for integrated circuits

Power harvesting for integrated circuits

Magnetoresistive random access memory (MRAM) bit cell with a narrow write window distribution

Leakage power management with NDR isolation devices

Interconnects, inductors, transformers, and power architectures for circuits

CFET architecture for balancing logic library and SRAM bitcell

SRAM and periphery specialized device sensors

SRAM and periphery specialized device sensors

ESD/antenna diodes for through-silicon vias

Mixed diffusion break for cell design

Reversing the effects of hot carrier injection and bias threshold instability in SRAMs

Superconductive integrated circuit devices with on-chip testing

Substrates and transistors with 2D material channels on 3D geometries

Parameterized superconducting multi-row circuit

VLSI TECHNOLOGY INC

Reduced switching noise output buffer using diode for quick turn-off

Digital output buffer and method with slew rate control and reduced crowbar current

Semiconductor FET structures with slew-rate control

KAWA JAMIL

N-channel and p-channel finFET cell architecture

N-channel and P-channel finFET cell architecture with inter-block insulator

SU QING

ESD/antenna diodes for through-silicon vias

ARTISAN COMPONENTS INC

Voltage tolerant input/output circuit

MOROZ VICTOR

Method and apparatus for floating or applying voltage to a well of an integrated circuit