Inventor

KAO YU-HSIANG

TW7 patents

⚠️ This page may combine multiple inventors who share the name “KAO YU-HSIANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TAIWAN SEMICONDUCTOR MFG

2 patents

US8898600B2Nov 25, 2014

Layout optimization for integrated design

TAIWAN SEMICONDUCTOR MFG3 citations62

US9292645B2Mar 22, 2016

Layout optimization for integrated circuit design

TAIWAN SEMICONDUCTOR MFG0 citations51

UNIV NAT TSING HUA

2 patents

US11865518B2Jan 9, 2024

Method for manufacturing electroless plating substrate and method for forming metal layer on surface of substrate

UNIV NAT TSING HUA0 citations59

US10828624B2Nov 10, 2020

Self-adsorbed catalyst composition, method for preparing the same and method for manufacturing electroless plating substrate

UNIV NAT TSING HUA0 citations48

TAIWAN SEMICONDUCTOR MFG CO LTD

2 patents

US9754073B2Sep 5, 2017

Layout optimization for integrated circuit design

TAIWAN SEMICONDUCTOR MFG CO LTD0 citations51

US9418196B2Aug 16, 2016

Layout optimization for integrated circuit design

TAIWAN SEMICONDUCTOR MFG CO LTD1 citations51

LU LEE-CHUNG

1 patent

US9553043B2Jan 24, 2017

Interconnect structure having smaller transition layer via

LU LEE-CHUNG0 citations41