Inventor
KOLPEKWAR ABHIJEET S
US3 patents
Patents
3 patentsUS9501592B1Nov 22, 2016
Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language
CADENCE DESIGN SYSTEMS INC7 citations79
US8732630B1May 20, 2014
Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language
CADENCE DESIGN SYSTEMS INC9 citations79
US8949753B1Feb 3, 2015
Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language
CADENCE DESIGN SYSTEMS INC6 citations68