Inventor

KRAUTSCHNEIDER WOLFGANG

DE46 patents

⚠️ This page may combine multiple inventors who share the name “KRAUTSCHNEIDER WOLFGANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KRAUTSCHNEIDER WOLFGANG

SIEMENS AG

Memory cell arrangement with vertical MOS transistors and the production process thereof

Memory cell configuration and method for its fabrication

Electrically programmable memory cell arrangement and method for its manufacture

Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells

Method of producing a read-only storage cell arrangement

Read-only-memory cell arrangement using vertical MOS transistors and gate dielectrics of different thicknesses and method for its production

Process of making a dram cell arrangement

Memory cell configuration and production process therefor

Method of operating a storage cell arrangement

DRAM cell arrangement and method for the production thereof

Electrically writable and erasable read-only memory cell arrangement and method for its production

Read-only memory cell arrangement and method for its production

DRAM cell array with dynamic gain memory cells

High density read only memory cell configuration and method for its production

DRAM cell arrangement and method for its manufacture

Ferroelectric memory cell arrangement

Arrangement with self-amplifying dynamic MOS transistor storage cells

Method for production of a read-only-memory cell arrangement having vertical MOS transistors

Method for production of a memory cell arrangement

Memory cell arrangement and process for manufacturing the same

Storage cell arrangement in which vertical MOS transistors have at least three different threshold voltages depending on stored data, and method of producing said arrangement

Method for the manufacturing a memory cell configuration

DRAM cell arrangement having dynamic self-amplifying memory cells, and method for manufacturing same

Integrated circuit arrangement having at least two mutually insulated components, and method for its production

Integrated CMOS circuit configuration, and production of same

Read-only memory cell array and process for manufacturing it

Method for manufacturing an electrically writeable and erasable read-only memory cell arrangement

Read-only memory cell arrangement

Method for DRAM cell arrangement and method for its production

DRAM cell arrangement and method for its production

Configuration for driving parallel lines in a memory cell configuration

Method for manufacturing an integrated circuit arrangement having at least one MOS transistor

Integrated circuit arrangement having at least one MOS transistor manufactured by use of a planar transistor layout

Signal sensing circuits for memory system using dynamic gain memory

INFINEON TECHNOLOGIES AG

Electrically programmable memory cell array, using charge carrier traps and insulation trenches

Memory cell configuration, method for fabricating it and methods for operating it

Method of producing a memory cell configuration

Integrated circuit configuration and method for manufacturing it

Mos transistor and dram cell configuration

Memory cell configuration

Method for operating a memory cell configuration having dynamic gain memory cells

Method for fabricating a memory cell

Integrated circuit configuration having at least one transistor and one capacitor, and method for fabricating it

Integrated dynamic memory cell having a small area of extent, and a method for its production

Arrangement with image sensors

TECHNISCHE UNIV HAMBURG

In-situ sensor