Inventor
PAPAZOVA VESSELINA K
US35 patents
⚠️ This page may combine multiple inventors who share the name “PAPAZOVA VESSELINA K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
27 patentsUS8775858B2Jul 8, 2014
Heterogeneous recovery in a redundant memory system
IBM297 citations99
US8832324B1Sep 9, 2014
First-in-first-out queue-based command spreading
IBM68 citations97
US9495231B2Nov 15, 2016
Reestablishing synchronization in a memory system
IBM6 citations84
US9146864B2Sep 29, 2015
Address mapping including generic bits for universal addressing independent of memory type
IBM12 citations84
US9318171B2Apr 19, 2016
Dual asynchronous and synchronous memory system
IBM8 citations83
US9142272B2Sep 22, 2015
Dual asynchronous and synchronous memory system
IBM9 citations83
US10628313B2Apr 21, 2020
Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cache
IBM3 citations73
US10628314B2Apr 21, 2020
Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cache
IBM2 citations73
US10489294B2Nov 26, 2019
Hot cache line fairness arbitration in distributed modular SMP system
IBM3 citations73
US10339064B2Jul 2, 2019
Hot cache line arbitration
IBM5 citations73
US10572385B2Feb 25, 2020
Granting exclusive cache access using locality cache coherency state
IBM2 citations72
US9852071B2Dec 26, 2017
Granting exclusive cache access using locality cache coherency state
IBM2 citations72
US9104564B2Aug 11, 2015
Early data delivery prior to error detection completion
IBM4 citations72
US8769335B2Jul 1, 2014
Homogeneous recovery in a redundant memory system
IBM3 citations63
US9092330B2Jul 28, 2015
Early data delivery prior to error detection completion
IBM2 citations62
US9037811B2May 19, 2015
Tagging in memory control unit (MCU)
IBM2 citations62
US9003127B2Apr 7, 2015
Storing data in a system memory for a subsequent cache flush
IBM3 citations62
US7934059B2Apr 26, 2011
Method, system and computer program product for preventing lockout and stalling conditions in a multi-node system with speculative memory fetching
IBM6 citations61
US9594646B2Mar 14, 2017
Reestablishing synchronization in a memory system
IBM0 citations52
US9535778B2Jan 3, 2017
Reestablishing synchronization in a memory system
IBM0 citations52
US10489292B2Nov 26, 2019
Ownership tracking updates across multiple simultaneous operations
IBM0 citations51
US10482015B2Nov 19, 2019
Ownership tracking updates across multiple simultaneous operations
IBM0 citations51
US9798663B2Oct 24, 2017
Granting exclusive cache access using locality cache coherency state
IBM1 citations51
US8001328B2Aug 16, 2011
Method and process for expediting the return of line exclusivity to a given processor through enhanced inter-node communications
IBM0 citations49
US9678873B2Jun 13, 2017
Early shared resource release in symmetric multiprocessing computer systems
IBM0 citations42
US7523267B2Apr 21, 2009
Method for ensuring fairness among requests within a multi-node computer system
IBM0 citations42
US10380020B2Aug 13, 2019
Achieving high bandwidth on ordered direct memory access write stream into a processor cache
IBM0 citations39
BLAKE MICHAEL A
4 patentsUS8423736B2Apr 16, 2013
Maintaining cache coherence in a multi-node, symmetric multiprocessing computer
BLAKE MICHAEL A10 citations83
US8762651B2Jun 24, 2014
Maintaining cache coherence in a multi-node, symmetric multiprocessing computer
BLAKE MICHAEL A4 citations72
US8990507B2Mar 24, 2015
Storing data in a system memory for a subsequent cache flush
BLAKE MICHAEL A0 citations51
US8131937B2Mar 6, 2012
Apparatus and method for improved data persistence within a multi-node system
BLAKE MICHAEL A0 citations40