Inventor

FARCY ALEXANDRE J

US19 patents

⚠️ This page may combine multiple inventors who share the name “FARCY ALEXANDRE J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FARCY ALEXANDRE J

INTEL CORP

Rotate instructions that complete execution either without writing or reading flags

Rotate instructions that complete execution either without writing or reading flags

Rotate instructions that complete execution either without writing or reading flags

Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution

Rotate instructions that complete execution without reading carry flag

Add instructions to add three source operands

Rotate instructions that complete execution either without writing or reading flags

Rotate instructions that complete execution either without writing or reading flags

Decoupling the number of logical threads from the number of simultaneous physical threads in a processor

Multiplication instruction for which execution completes without writing a carry flag

Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative execution

Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions

Method and apparatus for microarchitecture partitioning of execution clusters

GOPAL VINODH

Add instructions to add three source operands

Rotate instructions that complete execution without reading carry flag

KIM ILHYUN

Multi-level tracking of in-use state of cache lines

Hiding instruction cache miss latency by running tag lookups ahead of the instruction accesses

MERTEN MATTHEW C

Enhanced loop streaming detector to drive logic optimization

JOURDAN STEPHAN J

Forward-pass dead instruction identification and removal at run-time