Inventor
YANES JUAN ANTONIO
US14 patents
Patents
14 patentsUS6530043B1Mar 4, 2003
Write data error checking in a PCI Bus system
IBM24 citations92
US6084934AJul 4, 2000
Natural throttling of data transfer across asynchronous boundaries
IBM52 citations92
US6189117B1Feb 13, 2001
Error handling between a processor and a system managed by the processor
IBM20 citations91
US5944802AAug 31, 1999
Dynamic speed matching of host channel and device data transfers
IBM22 citations87
US6085285AJul 4, 2000
Intermixing different devices along a single data communication link by placing a strobe signal in a parity bit slot
IBM17 citations84
US6490644B1Dec 3, 2002
Limiting write data fracturing in PCI bus systems
IBM18 citations83
US6038613AMar 14, 2000
Prefetching and storing device work information from multiple data storage devices
IBM17 citations82
US6449678B1Sep 10, 2002
Method and system for multiple read/write transactions across a bridge system
IBM14 citations81
US6636913B1Oct 21, 2003
Data length control of access to a data bus
IBM12 citations73
US6535937B1Mar 18, 2003
Write command verification across a PCI bus system
IBM10 citations73
US5928375AJul 27, 1999
Method for enhancing data transmission in parity based data processing systems
IBM9 citations73
US6246726B1Jun 12, 2001
High speed digital data transmission by separately clocking and recombining interleaved data subgroups
IBM2 citations62
US6091783AJul 18, 2000
High speed digital data transmission by separately clocking and recombining interleaved data subgroups
IBM2 citations62
US6557087B1Apr 29, 2003
Management of PCI read access to a central resource
IBM4 citations61