Inventor
GOODWIN PAUL M
US22 patents
⚠️ This page may combine multiple inventors who share the name “GOODWIN PAUL M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
DIGITAL EQUIPMENT CORP
13 patentsUS5659713AAug 19, 1997
Memory stream buffer with variable-size prefetch depending on memory interleaving configuration
DIGITAL EQUIPMENT CORP114 citations97
US5586294ADec 17, 1996
Method for increased performance from a memory stream buffer by eliminating read-modify-write streams from history buffer
DIGITAL EQUIPMENT CORP89 citations96
US5388247AFeb 7, 1995
History buffer control to reduce unnecessary allocations in a memory stream buffer
DIGITAL EQUIPMENT CORP68 citations96
US5371870ADec 6, 1994
Stream buffer memory having a multiple-entry address history buffer for detecting sequential reads to initiate prefetching
DIGITAL EQUIPMENT CORP75 citations95
US5490113AFeb 6, 1996
Memory stream buffer
DIGITAL EQUIPMENT CORP45 citations92
US5461718AOct 24, 1995
System for sequential read of memory stream buffer detecting page mode cycles availability fetching data into a selected FIFO, and sending data without aceessing memory
DIGITAL EQUIPMENT CORP46 citations92
US5235693AAug 10, 1993
Method and apparatus for reducing buffer storage in a read-modify-write operation
DIGITAL EQUIPMENT CORP50 citations92
US5216672AJun 1, 1993
Parallel diagnostic mode for testing computer memory
DIGITAL EQUIPMENT CORP35 citations92
US5014273AMay 7, 1991
Bad data algorithm
DIGITAL EQUIPMENT CORP31 citations92
US5008886AApr 16, 1991
Read-modify-write operation
DIGITAL EQUIPMENT CORP37 citations92
US5452418ASep 19, 1995
Method of using stream buffer to perform operation under normal operation mode and selectively switching to test mode to check data integrity during system operation
DIGITAL EQUIPMENT CORP15 citations73
US5357529AOct 18, 1994
Error detecting and correcting apparatus and method with transparent test mode
DIGITAL EQUIPMENT CORP10 citations73
US5918029AJun 29, 1999
Bus interface slicing mechanism allowing for a control/data-path slice
DIGITAL EQUIPMENT CORP2 citations62
COMPAQ COMPUTER CORP
5 patentsUS6226709B1May 1, 2001
Memory refresh control system
COMPAQ COMPUTER CORP190 citations96
US6125429ASep 26, 2000
Cache memory exchange optimized memory organization for a computer system
COMPAQ COMPUTER CORP75 citations95
US6108752AAug 22, 2000
Method and apparatus for delaying victim writes in a switch-based multi-processor system to maintain data coherency
COMPAQ COMPUTER CORP74 citations95
US6077306AJun 20, 2000
Bus interface slicing mechanism allowing for a control/data path slice
COMPAQ COMPUTER CORP43 citations95
US6043987AMar 28, 2000
Printed circuit board having a well structure accommodating one or more capacitor components
COMPAQ COMPUTER CORP38 citations90