Inventor

WITEK KEITH E

US32 patents

⚠️ This page may combine multiple inventors who share the name “WITEK KEITH E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WITEK KEITH E

MOTOROLA INC

Method for growing an epitaxial layer of material using a high temperature initial growth phase and a low temperature bulk growth phase

Trench random access memory cell and method of formation

Method for forming trench transistor structure

Vertical transistor structure

Vertically stacked vertical transistors used to form vertical logic gate structures

Integrated circuit having both vertical and horizontal devices and process for making the same

Computerized facsimile (FAX) system and method of operation

Dynamic memory device having a vertical transistor

Vertically formed semiconductor random access memory device

Semiconductor memory device and method of formation

Method of formation of transistor and logic gates

Methods of formation of semiconductor composite gate dielectric having multiple incorporated atomic dopants

Vertical transistor having an underlying gate electrode contact

Method of forming a semiconductor structure having an air region

Vertically oriented DRAM structure

Semiconductor structure having an air region and method of forming the semiconductor structure

Method for forming a transistor having a dynamic connection between a substrate and a channel region

Split-gate vertically oriented EEPROM device and process

Static random access memory cell having a thin film transistor (TFT) pass gate connection to a bit line

Method for forming a vertically integrated dynamic memory cell

Method of formation of vertical transistor

Transistor and a capacitor used for forming a vertically stacked dynamic random access memory cell

Field effect transistor having control and current electrodes positioned at a planar elevated surface and method of formation

Capped shallow trench isolation and method of formation

Trench transistor structure comprising at least two vertical transistors

Method for forming vertical transistor structures having bipolar and MOS devices

Transistor useful for further vertical integration and method of formation

Method for forming a compact transistor structure

Method for forming a transistor and a capacitor for use in a vertically stacked dynamic random access memory cell

Method for forming a dynamic contact which can be either on or off or switched therebetween

Field effect transistor having control and current electrodes positioned at a planar elevated surface

(unassigned)

Memory cell having a plural transistor transmission gate and method of formation