Inventor

SUGIBAYASHI TADAHIKO

JP101 patents

⚠️ This page may combine multiple inventors who share the name “SUGIBAYASHI TADAHIKO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SUGIBAYASHI TADAHIKO

NEC CORP

Semiconductor memory device

Magnetic random access memory with improved data reading method

Magnetic random access memory including a cell array having a magneto-resistance element

Semiconductor integrated circuit and semiconductor integrated circuit device

Low power consumption semiconductor dynamic random access memory device by reusing residual electric charge on bit line pairs

Dynamic random access memory device having sense amplifier arrays selectively activated when associated memory cell sub-arrays are accessed

Integrated circuit device having step-down circuit for producing internal power voltage free from overshoot upon voltage drop of external power voltage

Semiconductor integrated circuit device equipped with substrate biasing system selectively powered from internal and external power sources

Dual port memory having a plurality of memory cell arrays for a high-speed operation

Power supply start up circuit for dynamic random access memory

Magnetic memory cell and magnetic random access memory using the same

Non-volatile magnetic memory

Semiconductor memory apparatus using tunnel magnetic resistance elements

Power-on circuit and resetting method

Semiconductor storage device and system using the same

Semiconductor memory device

Semiconductor memory device having redundancy memory circuit

Semiconductor memory device having main word decoder skipping defective address during sequential access and method of controlling thereof

Bootstrap circuit incorporated in semiconductor memory device for driving word lines

Magnetic memory cell, magnetic random access memory, and data read/write method for magnetic random access memory

Semiconductor memory device having dual word line configuration

Dynamic random access memory device having a parallel testing mode for producing arbitrary test pattern

Semiconductor integrated circuit device with internal voltage controlling circuit

Semiconductor integrated circuit device having voltage regulating unit for variable internal power voltage level

Power-on detecting circuit desirable for integrated circuit equipped with internal step-down circuit

Semiconductor memory device having sense amplifiers shared between open bit line less affected by adjacent ones

Semiconductor dynamic memory

Semiconductor storage device

Magnetic random access memory

Magnetic random access memory and operation method of the same

Resistance change semiconductor memory device and method of reading data with a first and second switch circuit

Magnetic random access memory

MRAM and operation method of the same

Magnetic random access memory

Magnetic random access memory and operating method of the same

Toggle-type magnetoresistive random access memory

Semiconductor memory device using tunneling magnetoresistive elements

Cache memory having a DRAM memory cell

Semiconductor integrated circuit having a MPU and a DRAM cache memory

Semiconductor memory device

Semiconductor memory device having reversing logic means

Magnetic-domain-wall-displacement memory cell and initializing method therefor

SAKIMURA NOBORU

Operation method of MRAM including correcting data for single-bit error and multi-bit error

Semiconductor storage device and its manufacturing method

MRAM having variable word line drive potential

Semiconductor storage device and method of operating the same

Nonvolatile latch circuit and logic circuit using the same

Nonvolatile latch circuit

SUZUKI TETSUHIRO

Non-volatile logic circuit

SUGIBAYASHI TADAHIKO

Magnetoresistive effect element and magnetic random access memory using the same