Inventor

DELL TIMOTHY J

US73 patents

⚠️ This page may combine multiple inventors who share the name “DELL TIMOTHY J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DELL TIMOTHY J

IBM

On-board scrubbing of soft errors memory module

System, method and storage medium for providing segment level sparing

Power management on a memory card having a signal processing element

Stackable memory card

Programmable burst length DRAM

Synchronous memory packaged in single/dual in-line memory module and method of fabrication

Memory card design with parity and ECC for non-parity and non-ECC systems

High bandwidth DRAM with low operating power modes

Self-initiated self-refresh mode for memory modules

Error protection power-on-self-test for memory cards having ECC on board

Method and apparatus for ECC bus protection in a computer system with non-parity memory

Memory card utilizing two wire bus

Memory card adapter insertable into a motherboard memory card socket comprising a memory card receiving socket having the same configuration as the motherboard memory card socket

Method and structure for providing error correction code within a system having SIMMs

Providing a memory device having a shared error feedback pin

System and method for error correction and detection in a memory system

Systems and methods for improving serviceability of a memory system

System, method and storage medium for providing fault detection and correction in a memory subsystem

System, method and storage medium for providing fault detection and correction in a memory subsystem

Dynamically replacing a failed chip

Apparatus and method for modifying signals from a CPU to a memory card

Reconfigurable I/O DRAM

Method and structure for providing error correction code for each byte on SIMM&#39;S

System and method for providing a high fault tolerant memory system

Method for making a memory card adapter insertable into a motherboard memory card socket comprising a memory card receiving socket having the same configuration as the motherboard memory card socket

Data bus structure for use with multiple memory storage and driver receiver technologies and a method of operating such structures

High speed and low cost SDRAM memory subsystem

Method and structure for providing error correction code and automatic parity sensing

Method and structure for providing error correction code and parity for each byte on SIMM&#39;s

Virtual grouping of memory

Implementing ECC redundancy using reconfigurable logic blocks

Self monitoring and self repairing ECC

Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code

Systems, methods and computer program products for utilizing a spare lane for additional checkbits

Memory margin management

Traffic and temperature based memory testing

Method and apparatus for addressing individual banks of DRAMs on a memory card

High bandwidth narrow I/O memory device with command stacking

Memory card utilizing two wire bus

Method and structure for providing automatic parity sensing

Performance optimization of read functions in a memory system

Selective error coding

Bank-level fault management in a memory system

Memory operation of paired memory devices

Memory data management

DELL TIMOTHY J

Cascade interconnect memory system with enhanced reliability

System, method and storage medium for providing fault detection and correction in a memory subsystem

System to improve error code decoding using historical information and associated methods

System, method and storage medium for providing fault detection and correction in a memory subsystem

CORDERO EDGAR R

Implementing memory performance management and enhanced memory reliability accounting for thermal conditions

Method and structure for providing error correction code for each byte on SIMM'S

Method and structure for providing error correction code and parity for each byte on SIMM's