Inventor

KELLOGG MARK W

US48 patents

⚠️ This page may combine multiple inventors who share the name “KELLOGG MARK W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KELLOGG MARK W

IBM

On-board scrubbing of soft errors memory module

High density memory module with in-line bus switches being enabled in response to read/write selection state of connected RAM banks to improve data bus performance

High density memory modules with improved data bus performance

System, method and storage medium for providing segment level sparing

High reliability memory module with a fault tolerant address and command bus

276-Pin buffered memory module with enhanced fault tolerance

Power management on a memory card having a signal processing element

Programmable burst length DRAM

Synchronous memory packaged in single/dual in-line memory module and method of fabrication

Memory card, computer system and method of operation for differentiating the use of read-modify-write cycles in operating and initializaiton modes

Method for performing a command cancel function in a DRAM

High reliability memory module with a fault tolerant address and command bus

System, method and storage medium for providing a serialized memory interface with a bus repeater

High bandwidth DRAM with low operating power modes

Self-initiated self-refresh mode for memory modules

Method and system for reducing an amount of power utilized by selecting a lowest power mode from a plurality of power modes

Selectable interface between memory controller and memory simms

Memory card utilizing two wire bus

Memory modules with voltage regulation and level translation

Captured synchronous DRAM fails in a working environment

System, method and storage medium for a multi-mode memory buffer device

Carrier for test, burn-in, and first level packaging

Reconfigurable I/O DRAM

276-pin buffered memory module with enhanced fault tolerance

High reliability memory module with a fault tolerant address and command bus

System, method and storage medium for providing data caching and data compression in a memory subsystem

Data bus structure for use with multiple memory storage and driver receiver technologies and a method of operating such structures

High speed and low cost SDRAM memory subsystem

Memory device having asymmetrical CAS to data input/output mapping and applications thereof

Synchronous dynamic random access memory device having memory command cancel function

Error correction code on add-on cards for writing portions of data words

High reliability memory module with a fault tolerant address and command bus

System, method and storage medium for a multi-mode memory buffer device

System, method and storage medium for a memory subsystem with positional read data latency

Carrier for test, burn-in, and first level packaging

276-pin buffered memory module with enhanced fault tolerance

276-pin buffered memory module with enhanced fault tolerance

Method and apparatus for addressing individual banks of DRAMs on a memory card

High bandwidth narrow I/O memory device with command stacking

High reliability memory module with a fault tolerant address and command bus

Memory card utilizing two wire bus

Narrow data width DRAM with low latency page-hit operations

System, method and storage medium for providing data caching and data compression in a memory subsystem

Memory device with programmable receivers to improve performance

System, method and storage medium for providing a serialized memory interface with a bus repeater

System, method and storage medium for providing data caching and data compression in a memory subsystem

GOWER KEVIN C

High reliability memory module with a fault tolerant address and command bus

Memory subsystem with positional read data latency