Inventor

OGILVIE CLARENCE R

US66 patents

⚠️ This page may combine multiple inventors who share the name “OGILVIE CLARENCE R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OGILVIE CLARENCE R

IBM

System for allocating bus bandwidth by assigning priority for each bus duration time slot to application using bus frame and bus duration

Memory card utilizing two wire bus

Logic power optimization algorithm

Method of controlling external models in system-on-chip verification

Pass gate multiplexer

Rounding normalizer for floating point arithmetic operations

Method for modifying the behavior of a state machine

Tree-type multiplexers and methods for configuring the same

System and method for allocating memory allocation bandwidth by assigning fixed priority of access to DMA machines and programmable priority to processing unit

Method and system for efficiently multiplying signed and unsigned variable width operands

Structure for a system and method of predicting power events in an intermittent power environment and dispatching computational operations of an integrated circuit accordingly

System for method of predicting power events in an intermittent power environment and dispatching computational operations of an integrated circuit accordingly

Method for system level protection of field programmable logic devices

Method of selectively building redundant logic structures to improve fault tolerance

Performance screen ring oscillator formed from multi-dimensional pairings of scan chains

FPGA powerup to known functional state

Determining relative amount of usage of data retaining device based on potential of charge storing device

FPGA powerup to known functional state

Method and system for controlling forwarding or terminating of a request at a bus interface based on buffer availability

Device and method to reduce power consumption in integrated semiconductor devices

Testable passgate logic circuits

Memory card with signal processing element

Memory card utilizing two wire bus

Chip performance monitoring system and method

Chip performance monitoring system and method

Auto-compensating temperature valve controller for electro-rheological fluid micro-channel cooled integrated circuit

Flexible performance screen ring oscillator within a scan chain

Performance screen ring oscillator formed from paired scan chains

Apparatus for performing real time caching utilizing an execution quantization timer and an interrupt controller

Asynchronous interface methods and apparatus

Method for increasing the manufacturing yield of programmable logic devices

System and method for dynamically executing a function in a programmable logic array

Determining history state of data based on state of partially depleted silicon-on-insulator

System and method for dynamically executing a function in a programmable logic array

FPGA powerup to known functional state

Method and system for ordering requests at a bus interface

Data processing in digital systems

System and method for dynamically executing a function in a programmable logic array

Digital binary array multipliers using inverting full adders

Structure and method to optimize computational efficiency in low-power environments

Design structure for estimating and/or predicting power cycle length, method of estimating and/or predicting power cycle length and circuit thereof

Determining relative amount of usage of data retaining device based on potential of charge storing device

CHARLEBOIS MARGARET R

Circuit design using design variable function slope sensitivity

Ring oscillator

HERZL ROBERT D

Structure for identifying and implementing flexible logic block logic for easy engineering changes

Minimizing impact of design changes for integrated circuit designs

BERNSTEIN KERRY

Electro-rheological micro-channel anisotropic cooled integrated circuits and methods thereof

GOODNOW KENNETH J

Power management architecture and method of modulating oscillator frequency based on voltage supply

BERHANU MALEDE W

Method, circuit, and design structure for capturing data across a pseudo-synchronous interface

BICKFORD JEANNE P

Adaptive power control using timing canonicals