Inventor
CHIAROT KEVIN ARTHUR
US7 patents
Patents
7 patentsUS6148394ANov 14, 2000
Apparatus and method for tracking out of order load instructions to avoid data coherency violations in a processor
IBM37 citations91
US6035394AMar 7, 2000
System for providing high performance speculative processing of complex load/store instructions by generating primitive instructions in the load/store unit and sequencer in parallel
IBM25 citations91
US6061785AMay 9, 2000
Data processing system having an apparatus for out-of-order register operations and method therefor
IBM24 citations90
US5721864AFeb 24, 1998
Prefetching instructions between caches
IBM37 citations90
US6332181B1Dec 18, 2001
Recovery mechanism for L1 data cache parity errors
IBM52 citations89
US5860150AJan 12, 1999
Instruction pre-fetching of a cache line within a processor
IBM17 citations81
US6622236B1Sep 16, 2003
Microprocessor instruction fetch unit for processing instruction groups having multiple branch instructions
IBM6 citations57