Inventor

PAPANDREOU NIKOLAOS

CH142 patents

⚠️ This page may combine multiple inventors who share the name “PAPANDREOU NIKOLAOS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAPANDREOU NIKOLAOS

IBM

Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory

Threshold voltage shifting at a lower bit error rate by intelligently performing dummy configuration reads

Mitigating read errors following programming in a multi-level non-volatile memory

Dynamically optimizing flash data retention or endurance based on data write frequency

Techniques for reducing read voltage threshold calibration in non-volatile memory

Hybrid read voltage calibration in non-volatile random access memory

Migrating data between block pools in a storage system

Block mode toggling using hybrid controllers

Techniques for retention and read-disturb aware health binning

Adaptive read voltage threshold calibration in non-volatile memory

State-dependent read voltage threshold adaptation for nonvolatile memory

Calculating corrective read voltage offsets in non-volatile random access memory

Reducing read disturb effect on partially programmed blocks of non-volatile memory

Error-correction encoding and decoding

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

Data encoding in solid-state storage apparatus

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

Extending useful life of a non-volatile memory by health grading

Enhanced temperature compensation for resistive memory cell circuits

Determining prefix codes for pseudo-dynamic data compression utilizing clusters formed based on compression ratio

Method and apparatus for faster determination of a cell state of a resistive memory cell using a parallel resistor

Multilevel programming of phase change memory

Reducing read errors by performing mitigation reads to blocks of non-volatile memory

Device for selecting a level for at least one read voltage

Write and retire pages in QLC NAND blocks

Mirroring data in write caches of a controller of a non-volatile memory

Proactive data placement in high density storage by a hybrid non-volatile storage controller

Balancing utilization of memory pools of physical blocks of differing storage densities

Adapting memory block pool sizes using hybrid controllers

Calibration of open blocks in NAND flash memory

System and method for optimizing Reed-Solomon decoder for errors and erasures

Error recovery of data in non-volatile memory during read

Updating corrective read voltage offsets in non-volatile random access memory

Managing memory block calibration based on priority levels

Block health estimation for wear leveling in non-volatile memories

Data placement in write cache architecture supporting read heat data separation

Relocating and/or re-programming blocks of storage space based on calibration frequency and resource utilization

Managing programming errors in NAND flash memory

Reducing unnecessary calibration of a memory unit for which the error count margin has been exceeded

Methods for read threshold voltage shifting in non-volatile memory

Calibration of open blocks in NAND flash memory

Background mitigation reads in a non-volatile memory system

Accelerating garbage collection of flushed logical erase blocks in non-volatile memory

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

Page-level health equalization

MITTELHOLZER THOMAS

Data encoding in solid-state storage devices

Encoding a data word for writing the encoded data word in a multi-level solid state memory

FREY URS

Determining cell-state in phase-change memory

ELEFTHERIOU EVANGELOS S

Programming multi-level phase change memory cells