Inventor
LIEN WAN-YIH
TW15 patents
⚠️ This page may combine multiple inventors who share the name “LIEN WAN-YIH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
VANGUARD INT SEMICONDUCT CORP
7 patentsUS6037216AMar 14, 2000
Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene process
VANGUARD INT SEMICONDUCT CORP95 citations97
US6124165ASep 26, 2000
Method for making openings in a passivation layer over polycide fuses using a single mask while forming reliable tungsten via plugs on DRAMs
VANGUARD INT SEMICONDUCT CORP40 citations92
US6080664AJun 27, 2000
Method for fabricating a high aspect ratio stacked contact hole
VANGUARD INT SEMICONDUCT CORP48 citations92
US6001717ADec 14, 1999
Method of making local interconnections for dynamic random access memory (DRAM) circuits with reduced contact resistance and reduced mask set
VANGUARD INT SEMICONDUCT CORP30 citations92
US6103623AAug 15, 2000
Method for fabricating a tungsten plug structure and an overlying interconnect metal structure without a tungsten etch back or CMP procedure
VANGUARD INT SEMICONDUCT CORP21 citations88
US6096579AAug 1, 2000
Method for controlling the thickness of a passivation layer on a semiconductor device
VANGUARD INT SEMICONDUCT CORP8 citations74
US6074952AJun 13, 2000
Method for forming multi-level contacts
VANGUARD INT SEMICONDUCT CORP13 citations73
WORLDWIDE SEMICONDUCTOR MFG
4 patentsUS6338993B1Jan 15, 2002
Method to fabricate embedded DRAM with salicide logic cell structure
WORLDWIDE SEMICONDUCTOR MFG34 citations92
US6136646AOct 24, 2000
Method for manufacturing DRAM capacitor
WORLDWIDE SEMICONDUCTOR MFG17 citations84
US6211091B1Apr 3, 2001
Self-aligned eetching process
WORLDWIDE SEMICONDUCTOR MFG17 citations83
US6303955B1Oct 16, 2001
Dynamic random access memory with slanted active regions
WORLDWIDE SEMICONDUCTOR MFG3 citations53
TAIWAN SEMICONDUCTOR MFG
3 patentsUS6673683B1Jan 6, 2004
Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions
TAIWAN SEMICONDUCTOR MFG42 citations92
US6876027B2Apr 5, 2005
Method of forming a metal-insulator-metal capacitor structure in a copper damascene process sequence
TAIWAN SEMICONDUCTOR MFG10 citations71
US7071478B2Jul 4, 2006
System and method for passing particles on selected areas on a wafer
TAIWAN SEMICONDUCTOR MFG4 citations61