Inventor
REDDY PRAVEEN S
US43 patents
⚠️ This page may combine multiple inventors who share the name “REDDY PRAVEEN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
36 patentsUS6725307B1Apr 20, 2004
Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system
IBM59 citations94
US6457085B1Sep 24, 2002
Method and system for data bus latency reduction using transfer size prediction for split bus designs
IBM22 citations92
US6449698B1Sep 10, 2002
Method and system for bypass prefetch data path
IBM39 citations92
US7818388B2Oct 19, 2010
Data processing system, method and interconnect fabric supporting multiple planes of processing nodes
IBM11 citations84
US7484131B2Jan 27, 2009
System and method for recovering from a hang condition in a data processing system
IBM12 citations84
US7474658B2Jan 6, 2009
Data processing system, method and interconnect fabric supporting concurrent operations of varying broadcast scope
IBM12 citations84
US6678814B2Jan 13, 2004
Method and apparatus for allocating data usages within an embedded dynamic random access memory device
IBM15 citations84
US6539487B1Mar 25, 2003
System for dynamically selecting maximum number of accessible banks of memory per cycle by monitoring actual power to each of the banks to determine the number of accessible banks
IBM17 citations84
US9058273B1Jun 16, 2015
Frequency determination across an interface of a data processing system
IBM9 citations83
US6553463B1Apr 22, 2003
Method and system for high speed access to a banked cache memory
IBM7 citations74
US6467030B1Oct 15, 2002
Method and apparatus for forwarding data in a hierarchial cache memory architecture
IBM10 citations74
US7430684B2Sep 30, 2008
Method to use fabric initialization to test functionality of all inter-chip paths between processors in system
IBM6 citations73
US7627738B2Dec 1, 2009
Request and combined response broadcasting to processors coupled to other processors within node and coupled to respective processors in another node
IBM7 citations72
US7380102B2May 27, 2008
Communication link control among inter-coupled multiple processing units in a node to respective units in another node for request broadcasting and combined response
IBM8 citations72
US11580058B1Feb 14, 2023
Hierarchical ring-based interconnection network for symmetric multiprocessors
IBM2 citations71
US7483428B2Jan 27, 2009
Data processing system, method and interconnect fabric supporting a node-only broadcast
IBM5 citations63
US7451231B2Nov 11, 2008
Data processing system, method and interconnect fabric for synchronized communication in a data processing system
IBM4 citations63
US7415030B2Aug 19, 2008
Data processing system, method and interconnect fabric having an address-based launch governor
IBM3 citations63
US6574719B2Jun 3, 2003
Method and apparatus for concurrently communicating with multiple embedded dynamic random access memory devices
IBM2 citations63
US11740872B2Aug 29, 2023
Detection of unintended dependencies in hardware designs with pseudo-random number generators
IBM0 citations62
US10394636B2Aug 27, 2019
Techniques for managing a hang condition in a data processing system with shared memory
IBM1 citations62
US9495314B2Nov 15, 2016
Determining command rate based on dropped commands
IBM2 citations62
US9495312B2Nov 15, 2016
Determining command rate based on dropped commands
IBM2 citations62
US7453816B2Nov 18, 2008
Method and apparatus for automatic recovery from a failed node concurrent maintenance operation
IBM4 citations62
US12099463B2Sep 24, 2024
Hierarchical ring-based interconnection network for symmetric multiprocessors
IBM0 citations61
US7917730B2Mar 29, 2011
Processor chip with multiple computing elements and external i/o interfaces connected to perpendicular interconnection trunks communicating coherency signals via intersection bus controller
IBM2 citations58
US7865650B2Jan 4, 2011
Processor with coherent bus controller at perpendicularly intersecting axial bus layout for communication among SMP compute elements and off-chip I/O elements
IBM2 citations58
US9575921B2Feb 21, 2017
Command rate configuration in data processing system
IBM0 citations52
US9251111B2Feb 2, 2016
Command rate configuration in data processing system
IBM1 citations52
US7886199B2Feb 8, 2011
Recovery from a hang condition in a data processing system
IBM1 citations52
US7809004B2Oct 5, 2010
Data processing system and processing unit having an address-based launch governor
IBM0 citations52
US6606680B2Aug 12, 2003
Method and apparatus for accessing banked embedded dynamic random access memory devices
IBM0 citations52
US6298416B1Oct 2, 2001
Method and apparatus for transmitting control signals within a hierarchial cache memory architecture for a data processing system
IBM1 citations52
US9122608B2Sep 1, 2015
Frequency determination across an interface of a data processing system
IBM0 citations51
US7873861B2Jan 18, 2011
Apparatus to use fabric initialization to test functionality of all inter-chip paths between processors in system
IBM1 citations51
US10642760B2May 5, 2020
Techniques for command arbitation in symmetric multiprocessor systems
IBM0 citations41
RAYTHEON CO
4 patentsUS6266702B1Jul 24, 2001
Method and apparatus to insert and extract data from a plurality of slots of data frames by using access table to identify network nodes and their slots for insertion and extraction data
RAYTHEON CO128 citations96
US6381647B1Apr 30, 2002
Method and system for scheduling network communication
RAYTHEON CO48 citations95
US6374314B1Apr 16, 2002
Method for managing storage of data by storing buffer pointers of data comprising a sequence of frames in a memory location different from a memory location for pointers of data not comprising a sequence of frames
RAYTHEON CO30 citations91
US6317415B1Nov 13, 2001
Method and system for communicating information in a network
RAYTHEON CO47 citations91