Inventor
JOSHI RAJIV VASANT
US30 patents
⚠️ This page may combine multiple inventors who share the name “JOSHI RAJIV VASANT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
28 patentsUS5955781ASep 21, 1999
Embedded thermal conductors for semiconductor chips
IBM218 citations99
US6100199AAug 8, 2000
Embedded thermal conductors for semiconductor chips
IBM61 citations96
US5901304AMay 4, 1999
Emulating quasi-synchronous DRAM with asynchronous DRAM
IBM76 citations96
US6030895AFeb 29, 2000
Method of making a soft metal conductor
IBM55 citations95
US5920486AJul 6, 1999
Parameterized cells for generating dense layouts of VLSI circuits
IBM150 citations95
US5897370AApr 27, 1999
High aspect ratio low resistivity lines/vias by surface diffusion
IBM89 citations94
US5731245AMar 24, 1998
High aspect ratio low resistivity lines/vias with a tungsten-germanium alloy hard cap
IBM52 citations94
US6335569B1Jan 1, 2002
Soft metal conductor and method of making
IBM24 citations92
US6151266ANov 21, 2000
Asynchronous multiport register file with self resetting write operation
IBM29 citations92
US6038260AMar 14, 2000
Method and apparatus for transposing differential signals onto a set of binary signals to increase the information-carrying capacity of the original set of signals
IBM29 citations92
US6018550AJan 25, 2000
Method and apparatus for transposing differential signals onto a set of binary signals to increase the information-carrying capacity of the original set of signals
IBM26 citations92
US5973529AOct 26, 1999
Pulse-to-static conversion latch with a self-timed control circuit
IBM47 citations92
US6285082B1Sep 4, 2001
Soft metal conductor
IBM28 citations91
US5877084AMar 2, 1999
Method for fabricating high aspect ratio low resistivity lines/vias by surface reaction
IBM17 citations91
US5812847ASep 22, 1998
Rule-based method for designing user interfaces for applications
IBM57 citations91
US6444565B1Sep 3, 2002
Dual-rie structure for via/line interconnections
IBM34 citations90
US6433436B1Aug 13, 2002
Dual-RIE structure for via/line interconnections
IBM22 citations90
US7911263B2Mar 22, 2011
Leakage current mitigation in a semiconductor device
IBM14 citations84
US6279144B1Aug 21, 2001
Provably correct storage arrays
IBM15 citations83
US6943105B2Sep 13, 2005
Soft metal conductor and method of making
IBM8 citations74
US10139446B2Nov 27, 2018
Massive multi-dimensionality failure analytics with smart converged bounds
IBM2 citations73
US5995425ANov 30, 1999
Design of provably correct storage arrays
IBM11 citations73
US5757879AMay 26, 1998
Tungsten absorber for x-ray mask
IBM9 citations72
US5856026AJan 5, 1999
High aspect ratio low resistivity lines/vias by surface diffusion
IBM9 citations68
US7232745B2Jun 19, 2007
Body capacitor for SOI memory description
IBM3 citations63
US5939898AAug 17, 1999
Input isolation for self-resetting CMOS macros
IBM6 citations62
US9256704B2Feb 9, 2016
Efficient deployment of table lookup (TLU) in an enterprise-level scalable circuit simulation architecture
IBM0 citations52
US7158604B1Jan 2, 2007
Method and apparatus for superimposing differential signals onto a set of binary signals to increase the information-carrying capacity of the original set of signals
IBM0 citations52