Inventor
CHO JAMES Y
US24 patents
⚠️ This page may combine multiple inventors who share the name “CHO JAMES Y”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
BROADCOM CORP
16 patentsUS6877076B1Apr 5, 2005
Memory controller with programmable configuration
BROADCOM CORP287 citations99
US6766389B2Jul 20, 2004
System on a chip for networking
BROADCOM CORP180 citations99
US6625685B1Sep 23, 2003
Memory controller with programmable configuration
BROADCOM CORP192 citations99
US7991922B2Aug 2, 2011
System on a chip for networking
BROADCOM CORP59 citations98
US7418534B2Aug 26, 2008
System on a chip for networking
BROADCOM CORP64 citations98
US6526483B1Feb 25, 2003
Page open hint in transactions
BROADCOM CORP179 citations97
US6633938B1Oct 14, 2003
Independent reset of arbiters and agents to allow for delayed agent reset
BROADCOM CORP20 citations93
US6816932B2Nov 9, 2004
Bus precharge during a phase of a clock signal to eliminate idle clock cycle
BROADCOM CORP23 citations92
US6449701B1Sep 10, 2002
Out of order associative queue in two clock domains
BROADCOM CORP34 citations92
US6681302B2Jan 20, 2004
Page open hint in transactions
BROADCOM CORP42 citations91
US7660931B2Feb 9, 2010
System on a chip for networking
BROADCOM CORP9 citations84
US7093052B2Aug 15, 2006
Bus sampling on one edge of a clock signal and driving on another edge
BROADCOM CORP7 citations74
US6678767B1Jan 13, 2004
Bus sampling on one edge of a clock signal and driving on another edge
BROADCOM CORP10 citations74
US6629218B2Sep 30, 2003
Out of order associative queue in two clock domains
BROADCOM CORP12 citations74
US6865633B2Mar 8, 2005
Independent reset of arbiters and agents to allow for delayed agent reset
BROADCOM CORP3 citations63
US7076582B2Jul 11, 2006
Bus precharge during a phase of a clock signal to eliminate idle clock cycle
BROADCOM CORP2 citations62
INTERGRAPH CORP
6 patentsUS5091846AFeb 25, 1992
Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
INTERGRAPH CORP170 citations99
US5255384AOct 19, 1993
Memory address translation system having modifiable and non-modifiable translation mechanisms
INTERGRAPH CORP114 citations98
US4933835AJun 12, 1990
Apparatus for maintaining consistency of a cache memory with a primary memory
INTERGRAPH CORP119 citations95
US4899275AFeb 6, 1990
Cache-MMU system
INTERGRAPH CORP78 citations95
US4884197ANov 28, 1989
Method and apparatus for addressing a cache memory
INTERGRAPH CORP62 citations95
US4860192AAug 22, 1989
Quadword boundary cache system
INTERGRAPH CORP112 citations95