Inventor
OSANAI TAKEKI
JP16 patents
⚠️ This page may combine multiple inventors who share the name “OSANAI TAKEKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TOSHIBA KK
8 patentsUS6360298B1Mar 19, 2002
Load/store instruction control circuit of microprocessor and load/store instruction control method
TOSHIBA KK29 citations84
US7607059B2Oct 20, 2009
Systems and methods for improved scan testing fault coverage
TOSHIBA KK10 citations83
US6389527B1May 14, 2002
Microprocessor allowing simultaneous instruction execution and DMA transfer
TOSHIBA KK17 citations80
US6327665B1Dec 4, 2001
Processor with power consumption limiting function
TOSHIBA KK7 citations73
US7240183B2Jul 3, 2007
System and method for detecting instruction dependencies in multiple phases
TOSHIBA KK5 citations58
US7346624B2Mar 18, 2008
Systems and methods for processing buffer data retirement conditions
TOSHIBA KK0 citations51
US7631149B2Dec 8, 2009
Systems and methods for providing fixed-latency data access in a memory system having multi-level caches
TOSHIBA KK1 citations48
US7689776B2Mar 30, 2010
Method and system for efficient cache locking mechanism
TOSHIBA KK0 citations42
IBM
7 patentsUS7302527B2Nov 27, 2007
Systems and methods for executing load instructions that avoid order violations
IBM47 citations92
US7376816B2May 20, 2008
Method and systems for executing load instructions that achieve sequential load consistency
IBM8 citations73
US7302530B2Nov 27, 2007
Method of updating cache state information where stores only read the cache state information upon entering the queue
IBM8 citations72
US7769985B2Aug 3, 2010
Load address dependency mechanism system and method in a high frequency, low power processor system
IBM2 citations62
US7730290B2Jun 1, 2010
Systems for executing load instructions that achieve sequential load consistency
IBM2 citations62
US7464242B2Dec 9, 2008
Method of load/store dependencies detection with dynamically changing address length
IBM6 citations62
US7363468B2Apr 22, 2008
Load address dependency mechanism system and method in a high frequency, low power processor system
IBM1 citations48