Inventor

SHU LEE-LEAN

US47 patents

⚠️ This page may combine multiple inventors who share the name “SHU LEE-LEAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHU LEE-LEAN

GSI TECHNOLOGY INC

Systems and methods of pipelined output latching involving synchronous memory arrays

Processing array device that performs one cycle full adder operation and bit line read/write logic features

Systems and methods of pipelined output latching involving synchronous memory arrays

Computational memory cell and processing array device using memory cells

Computational memory cell and processing array device using the memory cells for XOR and XNOR computations

Systems and methods of pipelined output latching involving synchronous memory arrays

Systems and methods of pipelined output latching involving synchronous memory arrays

Memory systems and methods involving high speed local address circuitry

Systems and methods involving data bus inversion memory circuitry, configuration and/or operation

Systems and methods involving phase detection with adaptive locking/detection features

Systems and methods involving propagating read and write address and data through multi-bank memory circuitry

Systems and methods of pipelined output latching involving synchronous memory arrays

Systems and methods involving data bus inversion memory circuitry, configuration and/or operation including data signals grouped into 10 bits and/or other features

Systems and methods involving data bus inversion memory circuitry, configuration and/or operation including data signals grouped into 10 bits and/or other features

Memory systems and methods involving high speed local address circuitry

Systems and methods involving phase detection with adaptive locking/detection features

Systems and methods including features of power supply noise reduction and/or power-saving for high speed delay lines

Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features

Systems and methods including clock features such as minimization of simultaneous switching outputs (SSO) effects involving echo clocks

Ultra low VDD memory cell with ratioless write port

Computational memory cell and processing array device with ratioless write port

Computational memory cell and processing array device using memory cells

Processing array device that performs one cycle full adder operation and bit line read/write logic features

Computational memory cell and processing array device using complementary exclusive or memory cells

System and method for refreshing a DRAM device

Computational memory cell and processing array device using the memory cells for XOR and XNOR computations

Computational memory cell and processing array device using memory cells

Systems and methods involving data bus inversion memory circuitry, configuration(s) and/or operation

Systems and methods involving multi-bank, dual-pipe memory circuitry

Storage array circuits and methods for computational memory cells

Computational memory cell and processing array device using the memory cells for XOR and XNOR computations

Computational memory cell and processing array device using memory cells

Processing array device that performs one cycle full adder operation and bit line read/write logic features

SONY ELECTRONICS INC

Binary weighted reference circuit for a variable impedance output buffer

Current mode test circuit for SRAM

SRAM with current-mode test read data path

ADVANCED MICRO DEVICES INC

Midpoint sense amplification scheme for a CMOS DRAM

Low power CMOS reference generator with low impedance driver

CMOS N-well bias generator and gating system

SHU LEE-LEAN

Systems and methods including clock features such as minimization of simultaneous switching outputs (SSO) effects involving echo clocks

System and method for refreshing a DRAM device

GIGA SEMICONDUCTOR INC

Data coherent logic for an SRAM device

System and method for testing multiple embedded memories

KIM JAE HYEONG

Systems and methods including features of power supply noise reduction and/or power-saving for high speed delay lines

SHU LEE LEAN

Static random access memory with self timed bit line equalization

SHYU JYN-BANG

Systems and methods involving phase detection with adaptive locking/detection features

(unassigned)

SRAM with current-mode read data path