P

Inventor

CHELLAPPAN SATHEESH

US22 patents
⚠️ This page may combine multiple inventors who share the name “CHELLAPPAN SATHEESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

18 patents
US9280510B2Mar 8, 2016

Inter-chip communications with link layer interface and protocol adaptor

INTEL CORP5 citations83
US10181975B2Jan 15, 2019

Override subsystems for rapid recovery from serial-link errors

INTEL CORP3 citations72
US10127162B2Nov 13, 2018

Efficient low cost on-die configurable bridge controller

INTEL CORP2 citations71
US10366017B2Jul 30, 2019

Methods and apparatus to offload media streams in host devices

INTEL CORP3 citations69
US10606772B2Mar 31, 2020

USB2 high speed connection for testing

INTEL CORP3 citations64
US10176132B2Jan 8, 2019

Configuration arbiter for multiple controllers sharing a link interface

INTEL CORP1 citations62
US11792446B2Oct 17, 2023

Methods and apparatus to reduce audio streaming latency between audio and gigabit ethernet subsystems

INTEL CORP0 citations61
US10834434B2Nov 10, 2020

Methods and apparatus to reduce audio streaming latency between audio and Gigabit Ethernet subsystems

INTEL CORP1 citations61
US10705142B2Jul 7, 2020

Device, system and method for providing on-chip test/debug functionality

INTEL CORP1 citations61
US12504911B2Dec 23, 2025

Method and system of standards-based audio function processing with reduced memory usage

INTEL CORP0 citations55
US12353240B2Jul 8, 2025

Selectable clock sources

INTEL CORP0 citations51
US11402893B2Aug 2, 2022

Low power data processing offload using external platform component

INTEL CORP0 citations51
US11308791B2Apr 19, 2022

Methods, systems and apparatus to use audio return path for functional safety validation

INTEL CORP0 citations51
US9904650B2Feb 27, 2018

Configuring a remote M-PHY

INTEL CORP0 citations51
US12335170B2Jun 17, 2025

Virtual physical circuit for on-chip communication

INTEL CORP0 citations50
US10417170B2Sep 17, 2019

Device, system and method for packet processing to facilitate circuit testing

INTEL CORP0 citations45
US10788533B2Sep 29, 2020

Systems and methods for bypass testing

INTEL CORP0 citations43
US10139445B2Nov 27, 2018

High speed I/O pinless structural testing

INTEL CORP0 citations42

RANGANATHAN SRIDHARAN

2 patents

VADIVELU KARTHI R

1 patent

LATTICE SEMICONDUCTOR CORP

1 patent