Inventor

GEORGE VARGHESE

US156 patents

⚠️ This page may combine multiple inventors who share the name “GEORGE VARGHESE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GEORGE VARGHESE

INTEL CORP

Virtual PCI device apparatus and method

Multiple operating frequencies in a processor

Systems and methods for improving cache efficiency and utilization

Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

Sparse optimizations for a matrix accelerator architecture

Disaggregation of SOC architecture

Method and apparatus for accurate on-die temperature measurement

Dynamically changing the performance of devices in a computer platform

Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

Graphics processor operation scheduling for deterministic latency

Method and apparatus for processor bypass path to system memory

Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor

Method, apparatus, and system for increasing single core performance in a multi-core microprocessor

Method and apparatus for establishing safe processor operating points in connection with a secure boot

System and method for selecting a frequency and voltage combination from a table using a selection field and a read-only limit field

Method, apparatus, and system for optimizing frequency and performance in a multi-die microprocessor

Method, apparatus and system to dynamically choose an aoptimum power state

Selective interrupt delivery to multiple processors having independent operating systems

Selective interrupt delivery to multiple processors having independent operating systems

Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor

Method and apparatus for improved reliability and reduced power in a processor by automatic voltage control during processor idle states

Maintaining processor execution during frequency transitioning

Graphics processor data access and sharing

Systems and methods for cache optimization

Dot product operations on sparse matrix elements

Deferred correction of a single bit storage error in a cache tag array

Systems and methods for improving cache efficiency and utilization

Multi-tile architecture for graphics operations

Dynamic memory reconfiguration

Disaggregation of system-on-chip (SOC) architecture

Efficient data sharing for graphics data processing operations

Sparse optimizations for a matrix accelerator architecture

Disaggregation of System-On-Chip (SOC) architecture

Multi-tile memory management

Systolic disaggregation within a matrix accelerator architecture

Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration

Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

Instruction based control of memory attributes

Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor

Method, system, and apparatus for dynamically configuring the operating point utilized for thermal management of an integrated circuit

Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs

Scalar core integration

Method, apparatus and system to dynamically choose an optimum power state

Cache structure and utilization

Method and apparatus for executing a long latency instruction to delay the restarting of an instruction fetch unit

ST MICROELECTRONICS INC

Self-programmable bidirectional buffer circuit and method

Self-programmable bidirectional buffer circuit and method

JAHAGIRDAR SANJEEV

Method and apparatus for powered off processor core mode

Technique for preserving cached information during a low power mode