Inventor · disambiguated record
Jorge Regolini
Also filed as: REGOLINI JORGE · REGOLINI JORGE L · REGOLINI JORGE LUIS
8 granted patents·2 pending applications·134 citations·filing 1991–2010
86Inventor score
Top patents by PatentIndex Score
10 records- 0178US5876796AProcess for selectively depositing a refractory metal silicide on silicon, and silicon wafer metallized using this processFRANCE TELECOM·Filed 1996·Granted Mar 2, 1999·44 cites·21 claims
- 0274US6316818B1Vertical bipolar transistor including an extrinsic base with reduced roughness, and fabrication processST MICROELECTRONICS SA·Filed 1999·Granted Nov 13, 2001·30 cites·3 claims
- 0370US7187038B2Semiconductor device with MOS transistors with an etch-stop layer having an improved residual stress level and method for fabricating such a semiconductor deviceST MICROELECTRONICS SA·Filed 2003·Granted Mar 6, 2007·17 cites·11 claims
- 0461US5252181AMethod for cleaning the surface of a substrate with plasmaAUTONOME DE DROIT PUBLIC FRANC·Filed 1991·Granted Oct 12, 1993·36 cites·7 claims
- 0551US2007251444A1PEALD Deposition of a Silicon-Based MaterialST MICROELECTRONICS SA·Filed 2007·Application pending·0 cites
- 0648US2010289107A1Photodiode with interfacial charge control by implantation and associated processST MICROELECTRONICS SA·Filed 2010·Application pending·0 cites
- 0745US8283707B2Reduction of threshold voltage instabilities in a MOS transistorREGOLINI JORGE·Filed 2007·Granted Oct 9, 2012·0 cites·22 claims
- 0844US8410570B2Photodiode with interfacial charge control and associated processREGOLINI JORGE·Filed 2010·Granted Apr 2, 2013·0 cites·18 claims
- 0937US6723610B2Vertical bipolar transistor including an extrinsic base with reduced roughness, and fabrication processST MICROELECTRONICS SA·Filed 2001·Granted Apr 20, 2004·0 cites·9 claims
- 1034US6465332B1Method of making MOS transistor with high doping gradient under the gateST MICROELECTRONICS SA·Filed 1998·Granted Oct 15, 2002·7 cites·12 claims
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