Inventor

LOPATIN SERGEY D

US69 patents

⚠️ This page may combine multiple inventors who share the name “LOPATIN SERGEY D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LOPATIN SERGEY D

ADVANCED MICRO DEVICES INC

Manufacturing method for semiconductor metalization barrier

Apparatus and method of encapsulated copper (Cu) Interconnect formation

Semiconductor metalization barrier

Method of forming copper sulfide for memory cell

Conformal atomic liner layer in an integrated circuit interconnect

Semiconductor catalytic layer and atomic layer deposition thereof

Method of copper interconnect formation using atomic layer copper deposition

Polymer memory device formed in via opening

Methods of forming passive layers in organic memory cells

Implantation for the formation of CuX layer in an organic memory device

Method of implantation after copper seed deposition

Selective formation of top memory electrode by electroless formation of conductive materials

Method of encapsulated copper (Cu) interconnect formation

Graded compound seed layers for semiconductors

Graded compound seed layers for semiconductors

Laminated conductive lines and methods of forming the same

Seedless barrier layers in integrated circuits and a method of manufacture therefor

Method of enhanced fill of vias and trenches

Post-CMP-Cu deposition and CMP to eliminate surface voids

Method for low stress plating of semiconductor vias and channels

Method for ramped current density plating of semiconductor vias and trenches

Low resistivity semiconductor barrier layer manufacturing method

Time ramped method for plating of high aspect ratio semiconductor vias and channels

Low resistivity semiconductor barrier layers and manufacturing method therefor

Sidewall formation for high density polymer memory element array

Silicon containing material for patterning polymeric memory element

Amorphous and gradated barrier layer for integrated circuit interconnects

Method of copper interconnect formation using atomic layer copper deposition and a device thereby formed

Implanted barrier layer to improve line reliability and method of forming same

Manufacturing a conformal atomic liner layer in an integrated circuit interconnect

Cu/Sn/Pd activation of a barrier layer for electroless CU deposition

Superconductor barrier layer for integrated circuit interconnects

SO2 treatment of oxidized CuO for copper sulfide formation of memory element growth

Multi-cell organic memory element and methods of operating and fabricating

CuS formation by anodic sulfide passivation of copper surface

Manufacturing seedless barrier layers in integrated circuits

Method of forming an adhesion layer with an element reactive with a barrier layer

Non-planar copper alloy target for plasma vapor deposition systems

Method of manufacturing an amorphized barrier layer for integrated circuit interconnects

Variable grain size in conductors for semiconductor vias and trenches

Amorphized barrier layer for integrated circuit interconnects

APPLIED MATERIALS INC

Anode structure with binders for silicon and stabilized lithium metal powder

Nucleation and growth of tin particles into three dimensional composite active anode for lithium high capacity energy storage device

Silver under-layers for electroless cobalt alloys

LOPATIN SERGEY D

Porous three dimensional copper, tin, copper-tin, copper-tin-cobalt, and copper-tin-cobalt-titanium electrodes for batteries and ultra capacitors

Porous three dimensional copper, tin, copper-tin, copper-tin-cobalt, and copper-tin-cobalt-titanium electrodes for batteries and ultra capacitors

Nucleation and growth of tin particles into three dimensional composite active anode for lithium high capacity energy storage device

KLA TENCOR TECH CORP

Nano-electrode-array for integrated circuit interconnects

Method and apparatus for transistor sidewall salicidation

SPANSION LLC

Etch-back process for capping a polymer memory device