Inventor

BUYNOSKI MATTHEW S

US104 patents

⚠️ This page may combine multiple inventors who share the name “BUYNOSKI MATTHEW S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BUYNOSKI MATTHEW S

ADVANCED MICRO DEVICES INC

Double spacer FinFET formation

Method for forming fins in a FinFET device using sacrificial carbon layer

Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors

FinFET-based SRAM cell

Method for forming channels in a finfet device

Process for forming fully silicided gates

Damascene NiSi metal gate high-k transistor

Frontside SOI gettering with phosphorus doping

Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors

Method of forming multiple levels of patterned metallization

Method of forming a metal or metal nitride interface layer between silicon nitride and copper

Polymer memory device formed in via opening

Implantation for the formation of CuX layer in an organic memory device

Method(s) facilitating formation of memory cell(s) and patterned conductive

Method of implantation after copper seed deposition

Low dielectric metal silicide lined interconnection system

Doping of thin amorphous silicon work function control layers of MOS gate electrodes

Method of forming low dielectric semiconductor device with rigid, metal silicide lined interconnection system

Low dielectric semiconductor device with rigid, conductively lined interconnection system

Low dielectric semiconductor device with rigid lined interconnection system

Bar field effect transistor

Field effect transistor with higher mobility

Self aligned damascene gate

Planar polymer memory device

Method for manufacturing a memory element

Self assembly of conducting polymer for formation of polymer memory cell

Laminated conductive lines and methods of forming the same

Metal gate with PVD amorphous silicon layer and barrier layer for CMOS devices and method of making with a replacement gate process

Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process

Semiconductor devices utilizing differently composed metal-based in-laid gate electrodes

Metal gate with CVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process

Method of forming semiconductor devices with differently composed metal-based gate electrodes

Argon implantation after silicidation for improved floating-body effects

Metal gate with PVD amorphous silicon and silicide for CMOS devices and method of making the same with a replacement gate process

Metal gate with CVD amorphous silicon layer and silicide for CMOS devices and method of making with a replacement gate process

Metal gate with CVD amorphous silicon layer and a barrier layer for CMOS devices and method of making with a replacement gate process

Metal gate with PVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process

Time ramped method for plating of high aspect ratio semiconductor vias and channels

Method of forming transistors with self aligned damascene gate contact

Self-aligned source and drain extensions fabricated in a damascene contact and gate process

Leaky lower interface for reduction of floating body effect in SOI devices

Method of forming low dielectric tungsten lined interconnection system

Method of patterning field dielectric regions in a semiconductor device

Method for fabrication of a low resistivity MOSFET gate with thick metal on polysilicon

Method for fabrication of a low resistivity MOSFET gate with thick metal silicide on polysilicon

Transistor device with reduced hot carrier injection effects

Silicon containing material for patterning polymeric memory element

NAT SEMICONDUCTOR CORP

Method of fabricating conductive non-metallic self-passivating non-corrodable IC bonding pads

High voltage complementary NPN/PNP process

ADVANCED MICRO SERVICES INC

Method of making field effect transistor with higher mobility