Inventor

WANG PIN-CHIN CONNIE

US41 patents

⚠️ This page may combine multiple inventors who share the name “WANG PIN-CHIN CONNIE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG PIN-CHIN CONNIE

ADVANCED MICRO DEVICES INC

Method of manufacturing a semiconductor device having copper interconnects

Method of forming a metal or metal nitride interface layer between silicon nitride and copper

Graphoepitaxial conductor cores in integrated circuit interconnects

Method of promoting void free copper interconnects

Barrier metal oxide interconnect cap in integrated circuits

Seedless barrier layers in integrated circuits and a method of manufacture therefor

Method of enhanced fill of vias and trenches

Via formation in integrated circuit interconnects

Copper interconnects with improved electromigration resistance and low resistivity

Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers

Use of ta/tan for preventing copper contamination of low-k dielectric layers

Selective copper alloy deposition

Implanted barrier layer to improve line reliability and method of forming same

Manufacturing an integrated circuit with low solubility metal-conductor interconnect cap

Selective deposition in integrated circuit interconnects

Void eliminating seed layer and conductor core integrated circuit interconnects

Method for forming conductor reservoir volume for integrated circuit interconnects

Manufacturing seedless barrier layers in integrated circuits

Method of forming an adhesion layer with an element reactive with a barrier layer

Integrated circuit with low solubility metal-conductor interconnect cap

Method of performing a two stage anneal in the formation of an alloy interconnect

Method of manufacturing an integrated circuit with a dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers

Characterization of barrier layers in integrated circuit interconnects

Non-planar copper alloy target for plasma vapor deposition systems

Barrier-to-seed layer alloying in integrated circuit interconnects

Conductor reservoir volume for integrated circuit interconnects

Coherent alloy diffusion barrier for integrated circuit interconnects

Coherent carbide diffusion barrier for integrated circuit interconnects

Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers

Method of forming an electroless nucleation layer on a via bottom

Coherent diffusion barriers for integrated circuit interconnects

Electro-chemical metal alloying for semiconductor manufacturing

Method of determining barrier layer effectiveness for preventing metallization diffusion by forming a test specimen device and using a metal penetration measurement technique for fabricating a production semiconductor device and a test specimen device thereby formed

Gradated barrier layer in integrated circuit interconnects

Integrated circuit interconnect shunt layer

Annealing ambient in integrated circuit interconnects

Controlled anneal conductors for integrated circuit interconnects

Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition

Integration scheme for non-feature-size dependent cu-alloy introduction

UNIV LELAND STANFORD JUNIOR

Thin films having rock-salt-like structure deposited on amorphous surfaces

GLOBALFOUNDRIES INC

Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect