Inventor

MACHNICKI ERIK P

US52 patents

⚠️ This page may combine multiple inventors who share the name “MACHNICKI ERIK P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MACHNICKI ERIK P

APPLE INC

Secure bypass of low-level configuration in reconfiguration of a computing system

Security enclave processor power control

System on a chip with always-on processor

System on a chip with always-on processor

System on a chip with always-on processor which reconfigures SOC and supports memory-only communication mode

System on a chip with always-on processor

System on a chip with always-on processor which reconfigures SOC and supports memory-only communication mode

Edge-triggered interrupt conversion in a system employing level-sensitive interrupts

Systems and methods for coalescing interrupts

Method for asynchronous gating of signals between clock domains

Timebase synchronization

Power management of cache duplicate tags

Dynamic clock and power gating with decentralized wake-ups

Power control for cache structures

Interrupt timestamping

Race-free level-sensitive interrupt delivery using fabric delivered interrupts

System on a chip with always-on processor

System on a chip with always-on component with powered-down configurations to process audio samples

Coherence processing with pre-kill mechanism to avoid duplicated transaction identifiers

Thermal voltage margin recovery

Interrupt distribution scheme

Method and apparatus for determining tunable parameters to use in power and performance management

Numerically-controlled oscillator

Multi-tier switch interface unit arbiter

Reset extender for divided clock domains

Timebase synchronization

Clock generation using fixed dividers and multiplex circuits

Under voltage detection and performance throttling

Interfacing dynamic hardware power managed blocks and software power managed blocks

Interfacing dynamic hardware power managed blocks and software power managed blocks

Low energy processor for controlling operating states of a computer system

Configuration fuse data management in a partial power-on state

System for managing memory devices

MACHNICKI ERIK P

Mechanism for an efficient DLL training protocol during a frequency change

Adjusting a device clock source to reduce wireless communication interference

Memory read timing margin adjustment for a plurality of memory arrays according to predefined delay tables

Modifying performance parameters in multiple circuits according to a performance state table upon receiving a request to change a performance state

DLL having a different training interval during a voltage change

SIMON MOSHE B

Method and system for performing DMA in a multi-core system-on-chip using deadline-based scheduling

Method and system for distributing a global timebase within a system-on-chip having multiple clock domains

Size and retry programmable multi-synchronous FIFO

CRADLE TECHNOLOGIES INC

System and method for DMA transfer of data in scatter/gather mode

Method and system for performing parallel integer multiply accumulate operations on packed data

DE CESARE JOSH P

Interrupt distribution scheme

CRADLE TECHNOLOGIES

Method and system for performing parallel integer multiply accumulate operations on packed data

GULATI MANU

System on a chip (SOC) debug controllability

CRADLE IP LLC

Method and system for performing DMA in a multi-core system-on-chip using deadline-based scheduling

MILLET TIMOTHY J

Systems and method for hardware dynamic cache power management via bridge and power manager

YU JIANLIN

Integrated circuit having secure access to test modes

PAASKE TIMOTHY R

Power on reset detector