Inventor
DEJANOVIC THOMAS
US27 patents
⚠️ This page may combine multiple inventors who share the name “DEJANOVIC THOMAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ARISTA NETWORKS INC
10 patentsUS11139904B2Oct 5, 2021
Clock domain crossing buffer
ARISTA NETWORKS INC3 citations73
US11405323B2Aug 2, 2022
Method and network device for forwarding data packets
ARISTA NETWORKS INC1 citations62
US12598228B2Apr 7, 2026
System and a method for distributing information
ARISTA NETWORKS INC0 citations59
US11985200B2May 14, 2024
System and a method for distributing information
ARISTA NETWORKS INC0 citations59
US12526222B2Jan 13, 2026
Network devices with hardware accelerated table updates
ARISTA NETWORKS INC0 citations57
US12149431B2Nov 19, 2024
Network devices with hardware accelerated table updates
ARISTA NETWORKS INC0 citations57
US11895005B1Feb 6, 2024
Network devices with hardware accelerated table updates
ARISTA NETWORKS INC0 citations57
US11652698B2May 16, 2023
Virtual layer 1 (LI) connectivity across a network
ARISTA NETWORKS INC1 citations56
US11121790B2Sep 14, 2021
Latency reduction in ethernet frames
ARISTA NETWORKS INC0 citations56
US11005644B2May 11, 2021
Time stamp generation
ARISTA NETWORKS INC0 citations54
CISCO TECH IND
8 patentsUS6967926B1Nov 22, 2005
Method and apparatus for using barrier phases to limit packet disorder in a packet switching system
CISCO TECH IND67 citations96
US6111877AAug 29, 2000
Load sharing across flows
CISCO TECH IND68 citations96
US6832261B1Dec 14, 2004
Method and apparatus for distributed resequencing and reassembly of subdivided packets
CISCO TECH IND107 citations95
US6603765B1Aug 5, 2003
Load sharing across flows
CISCO TECH IND24 citations92
US7009976B1Mar 7, 2006
Method and apparatus for using barrier phases to synchronize processes and components in a packet switching system
CISCO TECH IND18 citations91
US6934760B1Aug 23, 2005
Method and apparatus for resequencing of packets into an original ordering using multiple resequencing components
CISCO TECH IND47 citations90
US7016305B1Mar 21, 2006
Method and apparatus for distributing information within a packet switching system
CISCO TECH IND10 citations72
US7027397B1Apr 11, 2006
Method and apparatus for accumulating and distributing traffic and flow control information in a packet switching system
CISCO TECH IND0 citations52
CISCO TECH INC
5 patentsUS7269139B1Sep 11, 2007
Method and apparatus for an adaptive rate control mechanism reactive to flow control messages in a packet switching system
CISCO TECH INC35 citations92
US7046627B1May 16, 2006
Method and apparatus for accumulating and distributing traffic and flow control information in a packet switching system
CISCO TECH INC20 citations89
US7613200B1Nov 3, 2009
Method and apparatus using a random indication to map items to paths and to recirculate or delay the sending of a particular item when a destination over its mapped path is unreachable
CISCO TECH INC12 citations84
US7092393B1Aug 15, 2006
Method and apparatus for distributed reassembly of subdivided packets using multiple reassembly components
CISCO TECH INC17 citations82
US7051259B1May 23, 2006
Methods and apparatus for communicating time and latency sensitive information
CISCO TECH INC9 citations74
G2 MICROSYSTEMS PTY LTD
2 patentsUS7315281B2Jan 1, 2008
Location determination method and system for asset tracking devices
G2 MICROSYSTEMS PTY LTD117 citations96
US7313421B2Dec 25, 2007
GPS receiver having RF front end power management and simultaneous baseband searching of frequency and code chip offset
G2 MICROSYSTEMS PTY LTD46 citations91
METAMAKO GENERAL PTY LTD IN ITS CAPACITY AS GENERAL PARTNER OF METAMAKO TECH LP
2 patentsUS11075854B2Jul 27, 2021
System for reducing latency in network devices
METAMAKO GENERAL PTY LTD IN ITS CAPACITY AS GENERAL PARTNER OF METAMAKO TECH LP0 citations60
US11196834B2Dec 7, 2021
System and a method for distributing information
METAMAKO GENERAL PTY LTD IN ITS CAPACITY AS GENERAL PARTNER OF METAMAKO TECH LP0 citations57