Inventor

STEPHENS JR MICHAEL C

US56 patents

⚠️ This page may combine multiple inventors who share the name “STEPHENS JR MICHAEL C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STEPHENS JR MICHAEL C

STEPHENS JR MICHAEL C

Self-refresh adjustment in memory devices configured for stacked arrangements

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

Stack position determination in memory devices configured for stacked arrangements

Valid command detection based on stack position identifiers in memory devices configured for stacked arrangements

Memory devices with serially connected signals for stacked arrangements

Semiconductor memory device having calibration circuitry for dual-gate transistors associated with a memory array

Semiconductor memory device having calibration circuitry for dual-gate transistors associated with a memory array

Internal supply redundancy across memory devices configured for stacked arrangements

Serial searching in memory devices configured for stacked arrangements

Supply adjustment in memory devices configured for stacked arrangements

Internal supply testing in memory devices configured for stacked arrangements

Supply adjustment in memory devices configured for stacked arrangements

Latency adjustment based on stack position identifier in memory devices configured for stacked arrangements

Pad selection in memory devices configured for stacked arrangements

Dual-gate transistor control based on calibration circuitry

III HOLDINGS 2 LLC

Stack position determination in memory devices configured for stacked arrangements

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

Memory devices with serially connected signals for stacked arrangements

Valid command detection based on stack position identifiers in memory devices configured for stacked arrangements

Pad selection in memory devices configured for stacked arrangements

Self-refresh adjustment in memory devices configured for stacked arrangements

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

VANGUARD INT SEMICONDUCT CORP

Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices

Self-refresh test time reduction scheme

Internal charge pump voltage limit control

High-speed synchronous write control scheme

On-chip-generated supply voltage regulator with power-up mode

Dynamically adjustable on-chip supply voltage generation

Mock wordline scheme for timing control

Semiconductor memory device with improved read signal generation of data lines and assisted precharge to mid-level

Reticle option layer detection method

TEXAS INSTRUMENTS INC

Method and apparatus for preventing invalid operating modes and an application to synchronous memory devices

Method and apparatus for production testing of self-refresh operations and a particular application to synchronous memory devices

Array block level redundancy with steering logic

Output buffer with boost from voltage supplies

Dual receiver edge-triggered digital signal level detection system

ALLIANCE SEMICONDUCTOR CORP

Phase shift correction circuit for monolithic random access memory

Synchronous static random access memory having asynchronous test mode

Timing control circuit for synchronous static random access memory

Synchronous self-timed clock pulse circuit having improved power-up performance

Timing delay modulation scheme for integrated circuits

CYPRESS SEMICONDUCTOR CORP

Search engine device and method for generating output search responses from multiple input search responses

Result compare circuit and method for content addressable memory (CAM) device

Compare circuit and method for content addressable memory (CAM) device

JAMES DAVID V

Method and apparatus for restricted search operation in content addressable memory (CAM) devices