P

Inventor

ARANA LEONEL R

US25 patents
⚠️ This page may combine multiple inventors who share the name “ARANA LEONEL R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

17 patents
US7402515B2Jul 22, 2008

Method of forming through-silicon vias with stress buffer collars and resulting devices

INTEL CORP375 citations98
US7592697B2Sep 22, 2009

Microelectronic package and method of cooling same

INTEL CORP64 citations95
US7144299B2Dec 5, 2006

Methods and devices for supporting substrates using fluids

INTEL CORP13 citations84
US7462551B2Dec 9, 2008

Adhesive system for supporting thin silicon wafer

INTEL CORP17 citations81
US7243833B2Jul 17, 2007

Electrically-isolated interconnects and seal rings in packages using a solder preform

INTEL CORP9 citations74
US9659899B2May 23, 2017

Die warpage control for thin die assembly

INTEL CORP2 citations70
US9472519B2Oct 18, 2016

Forming sacrificial composite materials for package-on-package architectures and structures formed thereby

INTEL CORP1 citations62
US8009442B2Aug 30, 2011

Directing the flow of underfill materials using magnetic particles

INTEL CORP6 citations62
US7224050B2May 29, 2007

Plastic materials including dendrimers or hyperbranched polymers for integrated circuit packaging

INTEL CORP3 citations62
US12345932B2Jul 1, 2025

Die last and waveguide last architecture for silicon photonic packaging

INTEL CORP0 citations61
US11721631B2Aug 8, 2023

Via structures having tapered profiles for embedded interconnect bridge substrates

INTEL CORP0 citations59
US11373951B2Jun 28, 2022

Via structures having tapered profiles for embedded interconnect bridge substrates

INTEL CORP0 citations59
US7087451B2Aug 8, 2006

Microfabricated hot wire vacuum sensor

INTEL CORP3 citations57
US9793233B2Oct 17, 2017

Forming sacrificial composite materials for package-on-package architectures and structures formed thereby

INTEL CORP0 citations51
US12560771B2Feb 24, 2026

Die first fan-out architecture for electric and optical integration

INTEL CORP0 citations50
US9808875B2Nov 7, 2017

Methods of fabricating low melting point solder reinforced sealant and structures formed thereby

INTEL CORP0 citations50
US10078204B2Sep 18, 2018

Non-destructive 3-dimensional chemical imaging of photo-resist material

INTEL CORP0 citations39

MASSACHUSETTS INST TECHNOLOGY

2 patents

XU DINGYING

2 patents

GANESAN SANKA

1 patent

ARANA LEONEL R

1 patent

KULKARNI DEEPAK V

1 patent

SANE SANDEEP B

1 patent