Inventor

SALLESE KEVIN E

US18 patents

⚠️ This page may combine multiple inventors who share the name “SALLESE KEVIN E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SALLESE KEVIN E

IBM

Physical address management in solid state memory

Reducing read errors by performing mitigation reads to blocks of non-volatile memory

Read buffer architecture supporting integrated XOR-reconstructed and read-retry for non-volatile random access memory (NVRAM) systems

Determining a read apparent voltage infector page and infected page

Using content addressable memory to perform read-modify-write operations in non-volatile random access memory (NVRAM)

Calendar based flash command scheduler for dynamic quality of service scheduling and bandwidth allocations

Corrupt logical block addressing recovery scheme

Reducing effects of read array operations of read apparent voltage

Generating multi-plane reads to read pages on planes of a storage die for a page to read

Performing sub-logical page write operations in non-volatile random access memory (NVRAM) using pre-populated read-modify-write (RMW) buffers

Selectively performing multi-plane read operations in non-volatile memory

Physical address management in solid state memory by tracking pending reads therefrom

Physical address management in solid state memory

Physical address management in solid state memory

Read buffer architecture supporting integrated XOR-reconstructed and read-retry for non-volatile random access memory (NVRAM) systems

LATTICE SEMICONDUCTOR CORP

Diagonal interleaved parity calculator

Fast diagonal interleaved parity (DIP) calculator

Programmable logic device with a memory-based finite state machine