P

Inventor

MUKHOPADHYAY PARTHA

US23 patents
⚠️ This page may combine multiple inventors who share the name “MUKHOPADHYAY PARTHA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TOKYO ELECTRON LTD

21 patents
US12507447B2Dec 23, 2025

3D advanced transistor architecture integrated with source/drain spider design

TOKYO ELECTRON LTD0 citations62
US12501602B2Dec 16, 2025

3D hybrid memory using horizontally oriented conductive dielectric channel regions

TOKYO ELECTRON LTD0 citations62
US12457768B2Oct 28, 2025

Vertical transistors and methods for forming the same

TOKYO ELECTRON LTD0 citations62
US12439641B2Oct 7, 2025

Compact 3D design and connections with optimum 3D transistor stacking

TOKYO ELECTRON LTD0 citations62
US12408321B2Sep 2, 2025

3D horizontal memory cell with sequential 3D vertical stacking

TOKYO ELECTRON LTD0 citations62
US12349424B2Jul 1, 2025

Epitaxial semiconductor 3D horizontal nano sheet with high mobility 2D material channel

TOKYO ELECTRON LTD0 citations62
US12288747B2Apr 29, 2025

Multi-dimensional metal first device layout and circuit design

TOKYO ELECTRON LTD0 citations62
US12191210B2Jan 7, 2025

Formation of high density 3D circuits with enhanced 3D conductivity

TOKYO ELECTRON LTD0 citations62
US12176249B2Dec 24, 2024

3D nano sheet method using 2D material integrated with conductive oxide for high performance devices

TOKYO ELECTRON LTD0 citations62
US12114480B2Oct 8, 2024

Method of making of plurality of 3D vertical logic elements integrated with 3D memory

TOKYO ELECTRON LTD0 citations62
US12068205B2Aug 20, 2024

3D high density compact metal first approach for hybrid transistor designs without using epitaxial growth

TOKYO ELECTRON LTD0 citations62
US12009355B2Jun 11, 2024

3D stacked DRAM with 3D vertical circuit design

TOKYO ELECTRON LTD0 citations62
US11756836B2Sep 12, 2023

3D device layout and method using advanced 3D isolation

TOKYO ELECTRON LTD0 citations62
US12598734B2Apr 7, 2026

Method of making 3D memory stacking formation with high circuit density

TOKYO ELECTRON LTD0 citations52
US12538520B2Jan 27, 2026

3D high density self-aligned nanosheet device formation with efficient layout and design

TOKYO ELECTRON LTD0 citations52
US12464704B2Nov 4, 2025

Three-dimensional plurality of N horizontal memory cells with enhanced high performance circuit density

TOKYO ELECTRON LTD0 citations52
US12324206B2Jun 3, 2025

Semiconductor devices and methods of manufacturing thereof

TOKYO ELECTRON LTD0 citations52
US12218244B2Feb 4, 2025

Vertical transistor structures and methods utilizing selective formation

TOKYO ELECTRON LTD0 citations52
US12133387B2Oct 29, 2024

3D memory with conductive dielectric channel integrated with logic access transistors

TOKYO ELECTRON LTD0 citations52
US12131956B2Oct 29, 2024

Ultra dense 3D routing for compact 3D designs

TOKYO ELECTRON LTD0 citations52
US11830876B2Nov 28, 2023

Three-dimensional device with self-aligned vertical interconnection

TOKYO ELECTRON LTD0 citations52

ADVINUS THERAPEUTICS LTD

2 patents