Inventor

RESTLE PHILLIP J

US36 patents

⚠️ This page may combine multiple inventors who share the name “RESTLE PHILLIP J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RESTLE PHILLIP J

IBM

Variable resistance switch for wide bandwidth resonant global clock distribution

Duty cycle measurement circuit for measuring and maintaining balanced clock duty cycle

Resonant tree driven clock distribution grid

Built in self test circuit for measuring total timing uncertainty in a digital data path

Resonant tree driven clock distribution grid

Clock gated power supply noise compensation

Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation

Alpha particle shield for integrated circuit

Capacitive bend sensor

Tunable sector buffer for wide bandwidth resonant global clock distribution

Wide bandwidth resonant global clock distribution

Sequenced pulse-width adjustment in a resonant clocking circuit

Mitigation of on-chip supply voltage based on local and non-local (neighboring) cores&#39; supply voltage information and decision

Distributed phase detection for clock synchronization in multi-layer 3D stacks

Pulse-drive resonant clock with on-the-fly mode change

Pulse-drive resonant clock with on-the-fly mode change

Measurement of signal delays in microprocessor integrated circuits with sub-picosecond accuracy using frequency stepping

Measurement of signal delays in microprocessor integrated circuits with sub-picosecond accuracy using frequency stepping

Wiring-optimal method to route high performance clock nets satisfying electrical and reliability constraints

Clock buffers with pulse drive capability for power efficiency

Mitigation of on-chip supply voltage noise by monitoring slope of supply voltage based on time-based sensors

Setting switch size and transition pattern in a resonant clock distribution system

Setting switch size and transition pattern in a resonant clock distribution system

Setting switch size and transition pattern in a resonant clock distribution system

Mitigation of on-chip supply voltage noise by monitoring slope of supply voltage based on time-based sensors

Stitchable global clock for 3D chips

Stitchable global clock for 3D chips

Sequenced pulse-width adjustment in a resonant clocking circuit

Sequenced pulse-width adjustment in a resonant clocking circuit

Tunable sector buffer for wide bandwidth resonant global clock distribution

Hierarchical scalable high resolution digital programmable delay circuit

Clock buffers with pulse drive capability for power efficiency

Increasing the resolution of on-chip measurement circuits

Clock skew analysis and optimization

BOSE PRADIP

Vertical power budgeting and shifting for three-dimensional integration

BUCELOT THOMAS J

Synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network

Mitigation of on-chip supply voltage based on local and non-local (neighboring) cores' supply voltage information and decision