Inventor
PATHIKONDA CHAKRAPANI
US10 patents
Patents
10 patentsUS6208180B1Mar 27, 2001
Core clock correction in a 2/N mode clocking scheme
INTEL CORP181 citations98
US6268749B1Jul 31, 2001
Core clock correction in a 2/n mode clocking scheme
INTEL CORP28 citations92
US6061599AMay 9, 2000
Auto-configuration support for multiple processor-ready pair or FRC-master/checker pair
INTEL CORP31 citations92
US5802132ASep 1, 1998
Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
INTEL CORP33 citations92
US5862373AJan 19, 1999
Pad cells for a 2/N mode clocking scheme
INTEL CORP36 citations89
US6114887ASep 5, 2000
Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
INTEL CORP10 citations73
US6104219AAug 15, 2000
Method and apparatus for generating 2/N mode bus clock signals
INTEL CORP13 citations73
US5834956ANov 10, 1998
Core clock correction in a 2/N mode clocking scheme
INTEL CORP11 citations73
US5826067AOct 20, 1998
Method and apparatus for preventing logic glitches in a 2/n clocking scheme
INTEL CORP9 citations73
US5821784AOct 13, 1998
Method and apparatus for generating 2/N mode bus clock signals
INTEL CORP0 citations51