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Inventor
WIGHT JEFF
US
2 patents
Patents
2 patents
US6477674B1
Nov 5, 2002
Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements
INTEL CORP
105 citations
94
US5862373A
Jan 19, 1999
Pad cells for a 2/N mode clocking scheme
INTEL CORP
36 citations
89