Inventor

BURD GREGORY

US326 patents

⚠️ This page may combine multiple inventors who share the name “BURD GREGORY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BURD GREGORY

MARVELL INT LTD

Reduced-complexity decoding of parity check codes

Error correction coding for varying signal-to-noise ratio channels

LDPC encoder and decoder and method thereof

Cyclic redundancy check for out-of-order codewords

Error correction for storage devices

Adapting read reference voltage in flash memory device

Systems and methods for near-codeword detection and correction on the fly

Systems and methods for data-path protection

Methods and algorithms for joint channel-code decoding of linear block codes

LDPC encoder and method thereof

Parity check matrix and method of forming thereof

Address generator for LDPC encoder and decoder and method thereof

Embedded parity coding for data storage

Tensor product codes containing an iterative code

Architecture and control of reed-solomon error-correction decoding

Detection in the presence of media noise

Correcting errors in disk drive read back signals by iterating with the Reed-Solomon decoder

Detection in the presence of media noise

Method and apparatus for encoding/decoding data

Apparatus for encoding and decoding using sparse matrices

Systems and methods for configuring product codes for error correction in a hard disk drive

Systems and methods for joint decoding of sector and track error correction codes

Systems and methods for detection and correction of error floor events in iterative systems

Channel quality monitoring and method for qualifying a storage channel using an iterative decoder

Channel quality monitoring and method for qualifying a storage channel using an iterative decoder

VARNICA NEDELJKO

Low power LDPC decoding under defects/erasures/puncturing

Channel quality monitoring and method for qualifying a storage channel using an iterative decoder

Post-processing decoder of LDPC codes for improved error floors

Methods and apparatus for defect detection and correction via iterative decoding algorithms

Defect detection and correction via monitoring of syndromes and bit flips in decoder

Post-processing decoder of LDPC codes for improved error floors

BURD GREGORY

Method and system for compensating for adjacent tracks during reading of data

Method and system for compensating for adjacent tracks during reading of data

Implementing RAID in solid state memory

Methods and apparatus for error recovery in memory systems employing iterative codes

YEO ENGLING

Embedded parity coding for data storage

Embedded parity coding for data storage

Multi-parity tensor-product code for data channel

POO TZE LEI

Key generation techniques

Secure memory controlled access

AU SIU-HUNG FRED

Architecture and control of reed-solomon error-correction decoding

Cryptographic module with secure processor

YANG XUESHI

Determining threshold voltage distribution in flash memory

Determining threshold voltage distribution in flash memory

MARVELL WORLD TRADE LTD

Implementing RAID in solid state memory

Implementing raid in solid state memory

YANG SHAOHUA

Error correction system using an iterative product code

ZHANG YIFEI

QC-LDPC decoder with list-syndrome decoding

NANGARE NITIN

Method and system for compensating for adjacent tracks during reading of data

ZOU QIYUE

Write clock rephase for magnetic recording device