Inventor

VENKATESWARAN NATESAN

US55 patents

⚠️ This page may combine multiple inventors who share the name “VENKATESWARAN NATESAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VENKATESWARAN NATESAN

IBM

System and method of criticality prediction in statistical timing analysis

Timing optimization driven by statistical sensitivites

Dynamic voltage frequency scaling

Modeling multi-patterning variability with statistical timing

Systems and methods for correlated parameters in statistical static timing analysis

Hierarchical design of integrated circuits with multi-patterning requirements

Reducing runtime and memory requirements of static timing analysis

Systems and methods for correlated parameters in statistical static timing analysis

Parasitic extraction in an integrated circuit with multi-patterning requirements

Performing statistical timing analysis with non-separable statistical and deterministic variations

Methods for conserving memory in statistical static timing analysis

Method, system, and program product for accommodating spatially-correlated variation in a process parameter

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

Method for optimizing a VLSI floor planner using a path based hyper-edge representation

Multi-sided variations for creating integrated circuits

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

Modeling multi-patterning variability with statistical timing

Incremental common path pessimism analysis

Parallel access to running electronic design automation (EDA) application

Detecting and removing bias in subjective judging

Partial parameters and projection thereof included within statistical timing analysis

Modeling multi-patterning variability with statistical timing

Hierarchical design of integrated circuits with multi-patterning requirements

Parallel access to running electronic design automation (EDA) application

Method and apparatus for performing input/output floor planning on an integrated circuit design

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

Integrating manufacturing feedback into integrated circuit structure design

Multi-sided variations for creating integrated circuits

Multi-sided variations for creating integrated circuits

Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit

Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit

Parasitic extraction in an integrated circuit with multi-patterning requirements

Method of sharing and re-using timing models in a chip across multiple voltage domains

Partial parameters and projection thereof included within statistical timing analysis

Incremental common path pessimism analysis

Adaptive characterization and instantiation of timing abstracts

BUCK NATHAN C

Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence

Timing closure on multiple selective corners in a single statistical timing run

Integrating manufacturing feedback into integrated circuit structure design

System and method for efficient modeling of NPskew effects on static timing tests

SINHA DEBJIT

Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits

Method of performing timing analysis on integrated circuit chips with consideration of process variations

Method and apparatus for efficient incremental statistical timing analysis and optimization

FOREMAN ERIC A

Systems and methods for correlated parameters in statistical static timing analysis

Efficient slack projection for truncated distributions

KALAFALA KERIM

Method of measuring the impact of clock skew on slack during a statistical static timing analysis

System and method for performing static timing analysis in the presence of correlations between asserted arrival times

GLOBALFOUNDRIES INC

Dynamic and adaptive timing sensitivity during static timing analysis using look-up table

HEMMETT JEFFREY G

Performing statistical timing analysis with non-separable statistical and deterministic variations

BUCK NATHAN

Statistical clock cycle computation