Inventor

JANG JAE-MIN

KR59 patents

⚠️ This page may combine multiple inventors who share the name “JANG JAE-MIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JANG JAE-MIN

HYNIX SEMICONDUCTOR INC

Differential signal generation circuit

Duty cycle correction apparatus and semiconductor integrated circuit having the same

Phase mixer and delay locked loop including the same

Duty cycle correction circuit and semiconductor integrated circuit apparatus including the same

Semiconductor integrated circuit capable of overcoming clock signal jitter

Delay locked loop

Delay locked loop and delay locking method having burst tracking scheme

Voltage regulator for a synchronous clock system to reduce clock tree jitter

DLL circuit, update control apparatus in DLL circuit and update method of DLL circuit

Power noise detecting device and power noise control device using the same

Receiver of semiconductor memory apparatus

Output driving device

Semiconductor memory apparatus

Delay locked loop circuit and memory device having the same

Data output buffer circuit

Duty cycle correction circuit with reduced current consumption

Domain crossing circuit of a semiconductor memory apparatus

Receiver circuit

Semiconductor integrated circuit

Buffer circuit of semiconductor memory apparatus

SK HYNIX INC

Phase mixing circuit, and semiconductor apparatus and semiconductor system including the same

Semiconductor device and method for driving the same

Semiconductor memory device having pads

Duty cycle correction circuit and operation method thereof

Memory controller including memory manager for mapping buffer identifier to segment

Semiconductor memory device having pads

Duty cycle correction circuit and operation method thereof

Duty cycle correction circuit and operation method thereof

Semiconductor memory device having pads

Clock generation circuit and semiconductor apparatus including the same

Delay control circuit and clock generation circuit including the same

Phase locked loop

Input buffer circuit of semiconductor apparatus

KIM YONG-JU

Integrated circuit

Integrated circuit chip and transmitting /receiving system including the same

Internal supply voltage generating circuit and method for generating internal supply voltage

Semiconductor integrated circuit and method for driving the same

CHOI HAE-RANG

Latency control circuit, semiconductor memory device including the same, and method for controlling latency

Data input/output apparatus and method for semiconductor system

Phase locked loop

KIM YONG JU

On-die termination circuit

Internal control signal regulation circuit

On-die termination circuit

KIM HYUNG-SOO

Semiconductor memory device and method for generating output enable signal

Semiconductor IC device having power-sharing and method of power-sharing thereof

LEE JI-WANG

Input buffer circuit of semiconductor apparatus

Interface apparatus for semiconductor integrated circuit and interfacing method thereof

CHOI HAE RANG

Domain crossing circuit of a semiconductor memory apparatus

HYNIX SEMICONDUTOR INC

Voltage level comparison circuit of semiconductor memory apparatus, voltage adjustment circuit using voltage level comparison circuit, and semiconductor memory apparatus using the same

KIM HYUNG SOO

Data alignment circuit of semiconductor memory apparatus