Inventor

LIU HARRY HONGYUE

US45 patents

⚠️ This page may combine multiple inventors who share the name “LIU HARRY HONGYUE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU HARRY HONGYUE

SEAGATE TECHNOLOGY LLC

Asymmetric write current compensation using gate overdrive for resistive sense memory cells

Non-volatile memory read/write verify

Write current compensation using word line boosting circuitry

Memory cell with proportional current self-reference sensing

Bit set modes for a resistive sense memory cell array

Non-volatile memory cell with precessional switching

Voltage reference generation for resistive sense memory cells

NAND based resistive sense memory cell architecture

Asymmetric write current compensation using gate overdrive for resistive sense memory cells

Floating source line architecture for non-volatile memory

Defective bit scheme for multi-layer integrated memory device

Resistive sense memory array with partial block update capability

NAND based resistive sense memory cell architecture

Stuck-at defect condition repair for a non-volatile memory cell

Write current compensation using word line boosting circuitry

Write current compensation using word line boosting circuitry

Stuck-at defect condition repair for a non-volatile memory cell

Floating source line architecture for non-volatile memory

Hierarchical cross-point array of non-volatile memory

Floating source line architecture for non-volatile memory

NAND flash memory with integrated bit line capacitance

Resistive sense memory array with partial block update capability

Predictive thermal preconditioning and timing control for non-volatile memory cells

Compensating for variations in memory cell programmed state distributions

Semiconductor control line address decoding circuit

Current cancellation for non-volatile memory

Simultaneously writing multiple addressable blocks of user data to a resistive sense memory cell array

Data updating in non-volatile memory

Multi-stage parallel data transfer

Pipeline sensing using voltage storage elements to read non-volatile memory cells

CHEN YIRAN

Memory cell with proportional current self-reference sensing

Data updating in non-volatile memory

Memory hierarchy with non-volatile filter and victim caches

Voltage reference generation with selectable dummy regions

Predictive thermal preconditioning and timing control for non-volatile memory cells

Computer memory device with multiple interfaces

Predictive thermal preconditioning and timing control for non-volatile memory cells

Bit set modes for a resistive sense memory cell array

JUNG CHULMIN

Semiconductor control line address decoding circuit

Current cancellation for non-volatile memory

Hierarchical cross-point array of non-volatile memory

LU YONG

Asymmetric write current compensation using gate overdrive for resistive sense memory cells

Asymmetric write current compensation using gate overdrive for resistive sense memory cells

LI HAI

Write current compensation using word line boosting circuitry

WANG XIAOBIN

Non-volatile memory cell with precessional switching