Inventor

TROMBLEY MICHAEL R

US24 patents

⚠️ This page may combine multiple inventors who share the name “TROMBLEY MICHAEL R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TROMBLEY MICHAEL R

IBM

Variable stage entry/exit instruction pipeline

Memory system with apparatus and method to enable balanced bandwidth utilization

Independent control of DMA and I/O resources for mixed-endian computing systems

Error control coding methods for memories with subline accesses

Structure for handling data requests

Balanced bandwidth utilization

Memory access alignment in a double data rate (‘DDR’) system

Structure for data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency mode

Method and apparatus for reducing latency associated with read operations in a memory system

Structure for handling data access

Data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency mode

Memory access alignment in a double data rate (‘DDR’) system

Memory access alignment in a double data rate (‘DDR’) system

LASTRAS-MONTANO LUIS A

System for error decoding with retries and associated methods

System to improve error correction using variable latency and associated methods

BUCHMANN PETER

Error correcting code protected quasi-static bit communication on a high-speed bus

Error correcting code protected quasi-static bit communication on a high-speed bus

DELL TIMOTHY J

Cascade interconnect memory system with enhanced reliability

BUCHMANN PETER L

Power-on initialization and test for a cascade interconnect memory system

O'CONNOR JAMES A

Methods, systems, and computer program products for dynamic selective memory mirroring

JENKINS STEVEN K

Memory access alignment in a double data rate (‘DDR’) system

BALAKRISHNAN GANESH

Systems and methods for selectively closing pages in a memory

BAYSAH IRVING G

System to improve miscorrection rates in error control code through buffering and associated methods

ALLEN JR JAMES J

Structure for reducing latency associated with read operations in a memory system