Inventor

CHENG KUAN-LUN

TW439 patents

⚠️ This page may combine multiple inventors who share the name “CHENG KUAN-LUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHENG KUAN-LUN

TAIWAN SEMICONDUCTOR MFG CO LTD

Capacitance reduction for back-side power rail device

Multi-gate device and related methods

Methods of manufacturing inner spacers in a gate-all-around (GAA) FET through multi-layer spacer replacement

Semiconductor device on hybrid substrate and method of manufacturing the same

Packaged semiconductor devices including backside power rails and methods of forming the same

Epitaxial features confined by dielectric fins and spacers

Semiconductor structures and methods thereof

Tuning threshold voltage in nanosheet transitor devices

Semiconductor device structure

Semiconductor device structure and methods of forming the same

Method for manufacturing a FinFET device with a backside power rail and a backside self-aligned via by etching an extended source trench

Semiconductor devices with backside power rail and backside self-aligned via

Semiconductor device having backside via and method of fabricating thereof

Nano-sheet-based devices with asymmetric source and drain configurations

Backside PN junction diode

Method of forming high performance MOSFETs having varying channel structures

Integrated circuits with buried interconnect conductors

Self-aligned structure for semiconductor devices

Buried power rail and method forming same

Integrated circuit with a fin and gate structure and method making the same

Gap-insulated semiconductor device

Semiconductor device having nanosheet transistor and methods of fabrication thereof

Transistors with varying width nanosheet

FinFET structure with airgap and method of forming the same

Epitaxial features confined by dielectric fins and spacers

Semiconductor device with dummy fin and liner and method of forming the same

Semiconductor device and method of fabrication thereof

Multi-gate device and related methods

Fill fins for semiconductor devices

Methods of manufacturing gate-all-around (GAA) FETs through partial replacement of gate spacers

Method for manufacturing semiconductor device

Integrated circuit structure and method with hybrid orientation for FinFET

Semiconductor device

Semiconductor device and manufacturing method thereof

Fill fins for semiconductor devices

Self-aligned epitaxy layer

Buried interconnect conductor

Hybrid scheme for improved performance for P-type and N-type FinFETs

Semiconductor device and manufacturing method thereof

FinFET semiconductor structure having hybrid substrate and method of fabricating the same

Method for forming semiconductor device

Seam free isolation structures and method for making the same

Capacitance reduction for back-side power rail device

Gate isolation structure

Stacked multi-gate structure and methods of fabricating the same

Semiconductor device with air gaps and method of fabrication thereof

Integration of silicon channel nanostructures and silicon-germanium channel nanostructures

Gate-all-around device with trimmed channel and dipoled dielectric layer and methods of forming the same

TAIWAN SEMICONDUCTOR MFG

Semiconductor device having high drive current and method of manufacture therefor

TAIWAIN SEMICONDUCTOR MFG COMP

Method for manufacturing a semiconductor device having an improved disposable spacer