Inventor
NADIR JAMES
US12 patents
⚠️ This page may combine multiple inventors who share the name “NADIR JAMES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
11 patentsUS4257095AMar 17, 1981
System bus arbitration, circuitry and methodology
INTEL CORP169 citations98
US5517136AMay 14, 1996
Opportunistic time-borrowing domino logic
INTEL CORP73 citations95
US5210845AMay 11, 1993
Controller for two-way set associative cache
INTEL CORP75 citations95
US5737569AApr 7, 1998
Multiport high speed memory having contention arbitration capability without standby delay
INTEL CORP29 citations91
US5479641ADec 26, 1995
Method and apparatus for overlapped timing of cache operations including reading and writing with parity checking
INTEL CORP35 citations91
US5450565ASep 12, 1995
Circuit and method for selecting a set in a set associative cache
INTEL CORP22 citations91
US5339399AAug 16, 1994
Cache controller that alternately selects for presentation to a tag RAM a current address latch and a next address latch which hold addresses captured on an input bus
INTEL CORP55 citations89
US5530833AJun 25, 1996
Apparatus and method for updating LRU pointer in a controller for two-way set associative cache
INTEL CORP18 citations81
US5392417AFeb 21, 1995
Processor cycle tracking in a controller for two-way set associative cache
INTEL CORP7 citations73
US5367659ANov 22, 1994
Tag initialization in a controller for two-way set associative cache
INTEL CORP18 citations73
US5724547AMar 3, 1998
LRU pointer updating in a controller for two-way set associative cache
INTEL CORP7 citations65